coreboot-kgpe-d16/src/mainboard/google/rush_ryu/gpio.h
Jimmy Zhang 0ee0d92978 google/rush_ryu: dsi: Enable panel related vdd and clocks
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>

Change-Id: Ia10bf7ae3bde389e883970f9a6ee931c32b8172b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f26902364b6a453adb850abfb0c4ce9686e99b5d
Original-Change-Id: I68b92608098959cca14324bfc7e1e58389205989
Original-Reviewed-on: https://chromium-review.googlesource.com/226905
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9514
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10 20:42:47 +02:00

73 lines
2 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__
#define __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__
#include <gpio.h>
#include <base3.h>
/* Board ID definitions. */
enum {
BOARD_REV0 = BASE3(0, 0),
BOARD_REV1 = BASE3(0, 1),
BOARD_REV2 = BASE3(0, Z),
BOARD_REV3 = BASE3(1, 0),
BOARD_REV4 = BASE3(1, 1),
BOARD_REV5 = BASE3(1, Z),
BOARD_REV6 = BASE3(Z, 0),
BOARD_REV7 = BASE3(Z, 1),
BOARD_REV8 = BASE3(Z, Z),
BOARD_ID_PROTO_0 = BOARD_REV0,
BOARD_ID_PROTO_1 = BOARD_REV1,
BOARD_ID_PROTO_3 = BOARD_REV2,
BOARD_ID_EVT = BOARD_REV3,
BOARD_ID_DVT = BOARD_REV4,
BOARD_ID_PVT = BOARD_REV5,
BOARD_ID_MP = BOARD_REV6,
};
enum {
/* Board ID related GPIOS. */
BD_ID0 = GPIO(Q3),
BD_ID1 = GPIO(Q4),
/* LTE modem related GPIOs */
MODEM_RESET = GPIO(S3),
MODEM_PWR_ON = GPIO(S4),
MDM_DET = GPIO(V1),
/* Warm reset */
AP_SYS_RESET_L = GPIO(I5),
/* Write Protect */
SPI_1V8_WP_L = GPIO(R1),
WRITE_PROTECT_L = SPI_1V8_WP_L,
WRITE_PROTECT_L_INDEX = GPIO_R1_INDEX,
/* Power button - Depending on board id, maybe active high / low */
BTN_AP_PWR = GPIO(Q0),
POWER_BUTTON = BTN_AP_PWR,
POWER_BUTTON_INDEX = GPIO_Q0_INDEX,
/* Panel related GPIOs */
LCD_EN = GPIO(H5),
LCD_RST_L = GPIO(H3),
EN_VDD18_LCD = GPIO(X0),
EN_VDD_LCD = GPIO(BB6), /* P1/P3 board */
};
#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ */