08e7df9d5d
We've seen failures because the binaries were not being built into the image. In particular, the APCB is modified by the coreboot build process, so if the APCB isn't built correctly to support the correct number of SPDs, the build can fail. The mendocino FSP binaries are not yet pushed, so the build is currently pointing at the cezanne binaries. The mendocino FSP will be pushed when the mendocino chips are released for sale. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I31d11c5327416f4339930373c447531ae9f79d28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
29 lines
972 B
Text
29 lines
972 B
Text
CONFIG_TIMESTAMPS_ON_CONSOLE=y
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CONFIG_USE_AMD_BLOBS=y
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CONFIG_VENDOR_GOOGLE=y
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CONFIG_VGA_BIOS_ID="1002,1506"
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CONFIG_AMD_FWM_POSITION_INDEX=3
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CONFIG_VGA_BIOS=y
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CONFIG_CONSOLE_POST=y
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CONFIG_BOARD_GOOGLE_SKYRIM=y
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CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
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CONFIG_SPL_TABLE_FILE="3rdparty/amd_blobs/mendocino/PSP/TypeId0x55_SplTableBl_MDN.sbin"
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CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/mendocino/MdnGenericVbios.bin"
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CONFIG_FSP_M_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_M.fd"
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CONFIG_FSP_S_FILE="3rdparty/amd_blobs/cezanne/CEZANNE_S.fd"
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CONFIG_ASYNC_FILE_LOADING=y
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CONFIG_PSP_SOFTFUSE_BITS="34 28"
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CONFIG_UART_PCI_ADDR=0x0
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CONFIG_RUN_FSP_GOP=y
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CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
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CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
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CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
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CONFIG_DISPLAY_HOBS=y
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CONFIG_DISPLAY_UPD_DATA=y
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CONFIG_ADD_FSP_BINARIES=y
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CONFIG_POST_IO_PORT=0x80
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CONFIG_PAYLOAD_NONE=y
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CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
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CONFIG_DISPLAY_FSP_HEADER=y
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CONFIG_FATAL_ASSERTS=y
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CONFIG_DEBUG_SMI=y
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