cd39a41278
These are not northbridge functions. BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9e7d4c7554788a9fdbfdb90e6ead60060cc4c30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41264 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
54 lines
1.1 KiB
C
54 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/io.h>
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#include <reset.h>
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#include <soc/pci_devs.h>
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#include <soc/reset.h>
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#include <device/pci_ops.h>
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#include <soc/southbridge.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/reset.h>
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#include <fsp/util.h>
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#include <assert.h>
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void set_warm_reset_flag(void)
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{
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uint8_t ncp = inw(NCP_ERR);
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outb(NCP_ERR, ncp | NCP_WARM_BOOT);
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}
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int is_warm_reset(void)
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{
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return !!(inb(NCP_ERR) & NCP_WARM_BOOT);
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}
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void do_cold_reset(void)
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{
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/* De-assert and then assert all PwrGood signals on CF9 reset. */
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pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
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TOGGLE_ALL_PWR_GOOD);
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outb(RST_CMD | SYS_RST, SYS_RESET);
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}
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void do_warm_reset(void)
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{
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set_warm_reset_flag();
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/* Assert reset signals only. */
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outb(RST_CMD | SYS_RST, SYS_RESET);
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}
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void do_board_reset(void)
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{
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/* TODO: Would a warm_reset() suffice? */
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do_cold_reset();
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}
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void chipset_handle_reset(uint32_t status)
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{
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printk(BIOS_ERR, "Error: unexpected call to %s(0x%08x). Doing cold reset.\n",
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__func__, status);
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assert(0);
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do_cold_reset();
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}
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