e095c462dc
This option is not working so don't advertise it. Change-Id: I910162756a567289b2484a5445360a3197ae848c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
938 lines
28 KiB
Text
938 lines
28 KiB
Text
## SPDX-License-Identifier: GPL-2.0-only
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menu "Devices"
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config HAVE_VGA_TEXT_FRAMEBUFFER
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bool
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depends on !NO_GFX_INIT
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help
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Selected by graphics drivers that support legacy VGA text mode.
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config HAVE_VBE_LINEAR_FRAMEBUFFER
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bool
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depends on !NO_GFX_INIT
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help
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Selected by graphics drivers that can set up a VBE linear-framebuffer
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mode.
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config HAVE_LINEAR_FRAMEBUFFER
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bool
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depends on !NO_GFX_INIT
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help
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Selected by graphics drivers that can set up a generic linear
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framebuffer.
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config HAVE_FSP_GOP
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bool
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help
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Selected by drivers that support to run a blob that implements
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the Graphics Output Protocol (GOP).
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config MAINBOARD_NO_FSP_GOP
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bool
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help
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Selected by mainboards that do not have any graphics ports connected to the SoC.
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config MAINBOARD_HAS_NATIVE_VGA_INIT
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def_bool n
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help
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Selected by mainboards / drivers that provide native graphics
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init within coreboot.
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config MAINBOARD_FORCE_NATIVE_VGA_INIT
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def_bool n
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depends on MAINBOARD_HAS_NATIVE_VGA_INIT || MAINBOARD_HAS_LIBGFXINIT
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help
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Selected by mainboards / chipsets whose graphics driver can't or
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shouldn't be disabled.
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config VGA_ROM_RUN_DEFAULT
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def_bool n
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help
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Selected by mainboards whose graphics initialization depends on VGA OpROM.
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coreboot needs to load/execute legacy VGA OpROM in order to initialize GFX.
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config MAINBOARD_HAS_LIBGFXINIT
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def_bool n
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help
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Selected by mainboards that implement support for `libgfxinit`.
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Usually this requires a list of ports to be probed for displays.
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choice
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prompt "Graphics initialization"
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default NO_GFX_INIT if VGA_ROM_RUN_DEFAULT && PAYLOAD_SEABIOS
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default VGA_ROM_RUN if VGA_ROM_RUN_DEFAULT
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default MAINBOARD_DO_NATIVE_VGA_INIT
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default MAINBOARD_USE_LIBGFXINIT
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default RUN_FSP_GOP if INTEL_GMA_HAVE_VBT
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config MAINBOARD_DO_NATIVE_VGA_INIT
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bool "Use native graphics init"
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depends on MAINBOARD_HAS_NATIVE_VGA_INIT
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help
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Some mainboards, such as the Google Link, allow initializing the
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display without the need of a binary only VGA OPROM. Enabling this
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option may be faster, but also lacks flexibility in setting modes.
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config MAINBOARD_USE_LIBGFXINIT
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bool "Use libgfxinit"
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depends on MAINBOARD_HAS_LIBGFXINIT
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select HAVE_VGA_TEXT_FRAMEBUFFER
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select HAVE_LINEAR_FRAMEBUFFER
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select VGA if VGA_TEXT_FRAMEBUFFER
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help
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Use the SPARK library `libgfxinit` for the native graphics
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initialization. This requires an Ada toolchain.
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# TODO: Explain differences (if any) for onboard cards.
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config VGA_ROM_RUN
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bool "Run VGA Option ROMs"
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depends on PCI && (ARCH_X86 || ARCH_PPC64) && !MAINBOARD_FORCE_NATIVE_VGA_INIT
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select HAVE_VGA_TEXT_FRAMEBUFFER
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help
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Execute VGA Option ROMs in coreboot if found. This can be used
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to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
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payload.
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When using a SeaBIOS payload it runs all option ROMs with much
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more complete BIOS interrupt services available than coreboot,
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which some option ROMs require in order to function correctly.
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config RUN_FSP_GOP
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bool "Run a GOP driver"
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depends on HAVE_FSP_GOP && !MAINBOARD_NO_FSP_GOP
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select HAVE_LINEAR_FRAMEBUFFER
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help
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Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support
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to run a GOP blob. This option enables graphics initialization with
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such a blob.
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config NO_GFX_INIT
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bool "None"
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depends on !MAINBOARD_FORCE_NATIVE_VGA_INIT
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help
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Select this to not perform any graphics initialization in
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coreboot. This is useful if the payload (e.g. SeaBIOS) can
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initialize graphics or if pre-boot graphics are not required.
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endchoice
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config PRE_GRAPHICS_DELAY_MS
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int "Graphics initialization delay in ms"
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default 0
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depends on VGA_ROM_RUN
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help
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On some systems, coreboot boots so fast that connected monitors
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(mostly TVs) won't be able to wake up fast enough to talk to the
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VBIOS. On those systems we need to wait for a bit before executing
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the VBIOS.
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config ONBOARD_VGA_IS_PRIMARY
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bool "Use onboard VGA as primary video device"
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default n
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depends on PCI
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help
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This option lets you select which VGA device will be used
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to decode legacy VGA cycles. Not all chipsets implement this
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however. If not selected, the last adapter found will be used,
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else the onboard adapter is used.
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config S3_VGA_ROM_RUN
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bool "Re-run VGA Option ROMs on S3 resume"
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default y
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depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
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help
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Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
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When using a SeaBIOS payload it runs all option ROMs with much
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more complete BIOS interrupt services available than coreboot,
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which some option ROMs require in order to function correctly.
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If unsure, say N when using SeaBIOS as payload, Y otherwise.
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config ALWAYS_LOAD_OPROM
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def_bool n
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depends on VGA_ROM_RUN
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help
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Always load option ROMs if any are found. The decision to run
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the ROM is still determined at runtime, but the distinction
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between loading and not running comes into play for CHROMEOS.
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An example where this is required is that VBT (Video BIOS Tables)
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are needed for the kernel's display driver to know how a piece of
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hardware is configured to be used.
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config ALWAYS_RUN_OPROM
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def_bool n
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depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM
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help
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Always unconditionally run the option regardless of other
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policies.
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config ON_DEVICE_ROM_LOAD
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bool "Load Option ROMs on PCI devices"
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default n if PAYLOAD_SEABIOS
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default y if !PAYLOAD_SEABIOS
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depends on VGA_ROM_RUN
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help
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Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.
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If disabled, only Option ROMs stored in CBFS will be executed by
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coreboot. If you are concerned about security, you might want to
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disable this option, but it might leave your system in a state of
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degraded functionality.
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When using a SeaBIOS payload it runs all option ROMs with much
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more complete BIOS interrupt services available than coreboot,
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which some option ROMs require in order to function correctly.
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If unsure, say N when using SeaBIOS as payload, Y otherwise.
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choice
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prompt "Option ROM execution type"
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default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
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default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86
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depends on VGA_ROM_RUN
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config PCI_OPTION_ROM_RUN_REALMODE
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prompt "Native mode"
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bool
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depends on ARCH_X86 && !ARCH_RAMSTAGE_X86_64
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help
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If you select this option, PCI Option ROMs will be executed
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natively on the CPU in real mode. No CPU emulation is involved,
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so this is the fastest, but also the least secure option.
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(only works on x86/x64 systems)
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config PCI_OPTION_ROM_RUN_YABEL
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prompt "Secure mode"
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bool
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help
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If you select this option, the x86emu CPU emulator will be used to
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execute PCI Option ROMs.
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This option prevents Option ROMs from doing dirty tricks with the
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system (such as installing SMM modules or hypervisors), but it is
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also significantly slower than the native Option ROM initialization
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method.
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This is the default choice for non-x86 systems.
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endchoice
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config YABEL_PCI_ACCESS_OTHER_DEVICES
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prompt "Allow Option ROMs to access other devices"
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bool
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depends on PCI_OPTION_ROM_RUN_YABEL
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help
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Per default, YABEL only allows Option ROMs to access the PCI device
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that they are associated with. However, this causes trouble for some
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onboard graphics chips whose Option ROM needs to reconfigure the
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north bridge.
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config YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG
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prompt "Fake success on writing other device's config space"
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bool
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depends on YABEL_PCI_ACCESS_OTHER_DEVICES
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help
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By default, YABEL aborts when the Option ROM tries to write to other
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devices' config spaces. With this option enabled, the write doesn't
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follow through, but the Option ROM is allowed to go on.
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This can create issues such as hanging Option ROMs (if it depends on
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that other register changing to the written value), so test for
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impact before using this option.
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config YABEL_VIRTMEM_LOCATION
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prompt "Location of YABEL's virtual memory"
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hex
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depends on PCI_OPTION_ROM_RUN_YABEL
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default 0x1000000
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help
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YABEL requires 1MB memory for its CPU emulation. This memory is
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normally located at 16MB.
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config YABEL_DIRECTHW
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prompt "Direct hardware access"
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bool
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depends on PCI_OPTION_ROM_RUN_YABEL && ARCH_X86
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help
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YABEL consists of two parts: It uses x86emu for the CPU emulation and
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additionally provides a PC system emulation that filters bad device
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and memory access (such as PCI config space access to other devices
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than the initialized one).
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When choosing this option, x86emu will pass through all hardware
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accesses to memory and I/O devices to the underlying memory and I/O
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addresses. While this option prevents Option ROMs from doing dirty
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tricks with the CPU (such as installing SMM modules or hypervisors),
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they can still access all devices in the system.
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Enable this option for a good compromise between security and speed.
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config MULTIPLE_VGA_ADAPTERS
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bool
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default n
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menu "Display"
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depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
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config FRAMEBUFFER_SET_VESA_MODE
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prompt "Set framebuffer graphics resolution"
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bool
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default y if CHROMEOS
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depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
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select HAVE_VBE_LINEAR_FRAMEBUFFER
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help
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Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
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if FRAMEBUFFER_SET_VESA_MODE
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choice
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prompt "framebuffer graphics resolution"
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default FRAMEBUFFER_VESA_MODE_118
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help
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This option sets the resolution used for the coreboot framebuffer (and
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bootsplash screen).
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config FRAMEBUFFER_VESA_MODE_100
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bool "640x400 256-color"
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config FRAMEBUFFER_VESA_MODE_101
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bool "640x480 256-color"
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config FRAMEBUFFER_VESA_MODE_102
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bool "800x600 16-color"
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config FRAMEBUFFER_VESA_MODE_103
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bool "800x600 256-color"
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config FRAMEBUFFER_VESA_MODE_104
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bool "1024x768 16-color"
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config FRAMEBUFFER_VESA_MODE_105
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bool "1024x768 256-color"
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config FRAMEBUFFER_VESA_MODE_106
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bool "1280x1024 16-color"
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config FRAMEBUFFER_VESA_MODE_107
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bool "1280x1024 256-color"
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config FRAMEBUFFER_VESA_MODE_108
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bool "80x60 text"
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config FRAMEBUFFER_VESA_MODE_109
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bool "132x25 text"
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config FRAMEBUFFER_VESA_MODE_10A
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bool "132x43 text"
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config FRAMEBUFFER_VESA_MODE_10B
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bool "132x50 text"
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config FRAMEBUFFER_VESA_MODE_10C
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bool "132x60 text"
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config FRAMEBUFFER_VESA_MODE_10D
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bool "320x200 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_10E
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bool "320x200 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_10F
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bool "320x200 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_110
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bool "640x480 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_111
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bool "640x480 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_112
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bool "640x480 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_113
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bool "800x600 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_114
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bool "800x600 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_115
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bool "800x600 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_116
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bool "1024x768 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_117
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bool "1024x768 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_118
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bool "1024x768 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_119
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bool "1280x1024 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_11A
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bool "1280x1024 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_11B
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bool "1280x1024 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_USER
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bool "Manually select VESA mode"
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endchoice
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# Map the config names to an integer (KB).
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config FRAMEBUFFER_VESA_MODE
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prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
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hex
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default 0x100 if FRAMEBUFFER_VESA_MODE_100
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default 0x101 if FRAMEBUFFER_VESA_MODE_101
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default 0x102 if FRAMEBUFFER_VESA_MODE_102
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default 0x103 if FRAMEBUFFER_VESA_MODE_103
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default 0x104 if FRAMEBUFFER_VESA_MODE_104
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default 0x105 if FRAMEBUFFER_VESA_MODE_105
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default 0x106 if FRAMEBUFFER_VESA_MODE_106
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default 0x107 if FRAMEBUFFER_VESA_MODE_107
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default 0x108 if FRAMEBUFFER_VESA_MODE_108
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default 0x109 if FRAMEBUFFER_VESA_MODE_109
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default 0x10A if FRAMEBUFFER_VESA_MODE_10A
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default 0x10B if FRAMEBUFFER_VESA_MODE_10B
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default 0x10C if FRAMEBUFFER_VESA_MODE_10C
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default 0x10D if FRAMEBUFFER_VESA_MODE_10D
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default 0x10E if FRAMEBUFFER_VESA_MODE_10E
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default 0x10F if FRAMEBUFFER_VESA_MODE_10F
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default 0x110 if FRAMEBUFFER_VESA_MODE_110
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default 0x111 if FRAMEBUFFER_VESA_MODE_111
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default 0x112 if FRAMEBUFFER_VESA_MODE_112
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default 0x113 if FRAMEBUFFER_VESA_MODE_113
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default 0x114 if FRAMEBUFFER_VESA_MODE_114
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default 0x115 if FRAMEBUFFER_VESA_MODE_115
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default 0x116 if FRAMEBUFFER_VESA_MODE_116
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default 0x117 if FRAMEBUFFER_VESA_MODE_117
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default 0x118 if FRAMEBUFFER_VESA_MODE_118
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default 0x119 if FRAMEBUFFER_VESA_MODE_119
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default 0x11A if FRAMEBUFFER_VESA_MODE_11A
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default 0x11B if FRAMEBUFFER_VESA_MODE_11B
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default 0x118 if FRAMEBUFFER_VESA_MODE_USER
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endif # FRAMEBUFFER_SET_VESA_MODE
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config WANT_LINEAR_FRAMEBUFFER
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bool
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default y if CHROMEOS
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default y if PAYLOAD_EDK2
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default y if COREDOOM_SECONDARY_PAYLOAD
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choice
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prompt "Framebuffer mode"
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default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER
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default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && WANT_LINEAR_FRAMEBUFFER
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default VGA_TEXT_FRAMEBUFFER
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config VGA_TEXT_FRAMEBUFFER
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bool "Legacy VGA text mode"
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depends on HAVE_VGA_TEXT_FRAMEBUFFER
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help
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If this option is enabled, coreboot will initialize graphics in
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legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,
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switch to text mode before handing control to a payload.
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config VBE_LINEAR_FRAMEBUFFER
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bool "VESA framebuffer"
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depends on HAVE_VBE_LINEAR_FRAMEBUFFER
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help
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This option keeps the framebuffer mode set after coreboot finishes
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execution. If this option is enabled, coreboot will pass a
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framebuffer entry in its coreboot table and the payload will need a
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compatible driver.
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config GENERIC_LINEAR_FRAMEBUFFER
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bool "Linear \"high-resolution\" framebuffer"
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depends on HAVE_LINEAR_FRAMEBUFFER
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help
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This option enables a high-resolution, linear framebuffer. If this
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option is enabled, coreboot will pass a framebuffer entry in its
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coreboot table and the payload will need a compatible driver.
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endchoice
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# Workaround to have LINEAR_FRAMEBUFFER set in both cases
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# VBE_LINEAR_FRAMEBUFFER and GENERIC_LINEAR_FRAMEBUFFER.
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# `kconfig_lint` doesn't let us use the same name with
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# different texts in the choice above.
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config LINEAR_FRAMEBUFFER
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def_bool y
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depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER
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config BOOTSPLASH
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prompt "Show graphical bootsplash"
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bool
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depends on LINEAR_FRAMEBUFFER
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help
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This option shows a graphical bootsplash screen. The graphics are
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loaded from the CBFS file bootsplash.jpg.
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You can either specify the location and file name of the
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image in the 'General' section or add it manually to CBFS, using,
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for example, cbfstool.
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config LINEAR_FRAMEBUFFER_MAX_WIDTH
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int "Maximum width in pixels"
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depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT
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default 2560
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help
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Set the maximum width of the framebuffer. This may help with
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default fonts too tiny for high-resolution displays.
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config LINEAR_FRAMEBUFFER_MAX_HEIGHT
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int "Maximum height in pixels"
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depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT
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default 1600
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|
help
|
|
Set the maximum height of the framebuffer. This may help with
|
|
default fonts too tiny for high-resolution displays.
|
|
|
|
endmenu # "Display"
|
|
|
|
config PCI
|
|
bool
|
|
default n
|
|
|
|
if PCI
|
|
|
|
config NO_ECAM_MMCONF_SUPPORT
|
|
bool
|
|
default n
|
|
help
|
|
Disable the use of the Enhanced Configuration
|
|
Access mechanism (ECAM) method for accessing PCI config
|
|
address space.
|
|
|
|
config ECAM_MMCONF_SUPPORT
|
|
bool
|
|
default !NO_ECAM_MMCONF_SUPPORT
|
|
help
|
|
Enable the use of the Enhanced Configuration
|
|
Access mechanism (ECAM) method for accessing PCI config
|
|
address space.
|
|
|
|
config PCIX_PLUGIN_SUPPORT
|
|
bool
|
|
default y
|
|
|
|
config CARDBUS_PLUGIN_SUPPORT
|
|
bool
|
|
default y
|
|
|
|
config AZALIA_PLUGIN_SUPPORT
|
|
bool
|
|
default n
|
|
|
|
config AZALIA_LOCK_DOWN_R_WO_GCAP
|
|
def_bool n
|
|
depends on AZALIA_PLUGIN_SUPPORT
|
|
help
|
|
The GCAP register is implemented as R/WO (Read / Write Once) on some
|
|
HD Audio controllers, such as Intel 6-series PCHs. Select this option
|
|
to lock down the GCAP register after deasserting the controller reset
|
|
bit. Locking is done by reading GCAP and writing back the read value.
|
|
|
|
config PCIEXP_PLUGIN_SUPPORT
|
|
bool
|
|
default y
|
|
|
|
config ECAM_MMCONF_BASE_ADDRESS
|
|
hex
|
|
depends on ECAM_MMCONF_SUPPORT
|
|
|
|
config ECAM_MMCONF_BUS_NUMBER
|
|
int
|
|
depends on ECAM_MMCONF_SUPPORT
|
|
|
|
config ECAM_MMCONF_LENGTH
|
|
hex
|
|
depends on ECAM_MMCONF_SUPPORT
|
|
default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64
|
|
default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128
|
|
default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256
|
|
default 0x0
|
|
|
|
config PCI_ALLOW_BUS_MASTER
|
|
bool "Allow coreboot to set optional PCI bus master bits"
|
|
default y
|
|
help
|
|
For security reasons, bus mastering should be enabled as late as
|
|
possible. In coreboot, it's usually not necessary and payloads
|
|
should only enable it for devices they use. Since not all payloads
|
|
enable bus mastering properly yet, this option gives some sort of
|
|
"backwards compatibility" and is enabled by default to keep the
|
|
traditional behaviour for now. This is currently necessary, for
|
|
instance, for libpayload based payloads as the drivers don't enable
|
|
bus mastering for PCI bridges.
|
|
|
|
if PCI_ALLOW_BUS_MASTER
|
|
|
|
config PCI_SET_BUS_MASTER_PCI_BRIDGES
|
|
bool "PCI bridges"
|
|
default y
|
|
help
|
|
Let coreboot configure bus mastering for PCI bridges. Enabling bus
|
|
mastering for a PCI bridge also allows it to forward requests from
|
|
downstream devices. Currently, payloads ignore this and only enable
|
|
bus mastering for the downstream device. Hence, this option is needed
|
|
for compatibility until payloads are fixed.
|
|
|
|
config PCI_ALLOW_BUS_MASTER_ANY_DEVICE
|
|
bool "Any devices"
|
|
default y
|
|
select PCI_SET_BUS_MASTER_PCI_BRIDGES
|
|
help
|
|
Allow coreboot to enable PCI bus mastering for any device. The actual
|
|
selection of devices depends on the various PCI drivers in coreboot.
|
|
|
|
endif # PCI_ALLOW_BUS_MASTER
|
|
|
|
endif # PCI
|
|
|
|
if PCIEXP_PLUGIN_SUPPORT
|
|
|
|
config PCIEXP_COMMON_CLOCK
|
|
prompt "Enable PCIe Common Clock"
|
|
bool
|
|
default n
|
|
help
|
|
Detect and enable Common Clock on PCIe links.
|
|
|
|
config PCIEXP_ASPM
|
|
prompt "Enable PCIe ASPM"
|
|
bool
|
|
default n
|
|
help
|
|
Detect and enable ASPM (Active State Power Management) on PCIe links.
|
|
|
|
config PCIEXP_CLK_PM
|
|
prompt "Enable PCIe Clock Power Management"
|
|
bool
|
|
default n
|
|
help
|
|
Detect and enable Clock Power Management on PCIe.
|
|
|
|
config PCIEXP_L1_SUB_STATE
|
|
prompt "Enable PCIe ASPM L1 SubState"
|
|
bool
|
|
depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
|
|
default n
|
|
help
|
|
Detect and enable ASPM on PCIe links.
|
|
|
|
config PCIEXP_SUPPORT_RESIZABLE_BARS
|
|
prompt "Support PCIe Resizable BARs"
|
|
bool
|
|
depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
|
|
default n
|
|
help
|
|
When enabled, this will check PCIe devices for Resizable BAR support,
|
|
and if found, will use this to discover the preferred BAR sizes of
|
|
the device in preference over the traditional moving bits method. The
|
|
amount of address space given out to devices in this manner (since
|
|
it can range up to 8 EB) can be limited with the
|
|
PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS Kconfig setting below.
|
|
|
|
if PCIEXP_SUPPORT_RESIZABLE_BARS
|
|
|
|
config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS
|
|
int "Bits of address space to give to Resizable BARs"
|
|
range 20 63 # 1 MiB - 8 EiB
|
|
default 29 # 512 MiB
|
|
help
|
|
This is the maximum number of bits of address space to allocate for
|
|
PCIe devices with resizable BARs. For instance, if a device requests
|
|
30 bits of address space (1 GiB), but this field is set to 29, then
|
|
the device will only be allocated 29 bits worth of address space (512
|
|
MiB). Valid values range from 20 (1 MiB) to 63 (8 EiB); these come
|
|
from the Resizable BAR portion of the PCIe spec (7.8.6).
|
|
|
|
endif # PCIEXP_SUPPORT_RESIZABLE_BARS
|
|
|
|
config PCIEXP_LANE_ERR_STAT_CLEAR
|
|
prompt "Enable Clear PCIe Lane Error Status"
|
|
bool
|
|
default n
|
|
help
|
|
Clear the PCIe Lane Error Status at the end of link training.
|
|
|
|
config PCIEXP_HOTPLUG
|
|
prompt "Enable PCIe Hotplug Support"
|
|
bool
|
|
default n
|
|
help
|
|
Allocate resources for PCIe hotplug bridges
|
|
|
|
if PCIEXP_HOTPLUG
|
|
|
|
config PCIEXP_HOTPLUG_BUSES
|
|
int "PCI Express Hotplug Buses"
|
|
default 8 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 64
|
|
default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128
|
|
default 32
|
|
help
|
|
This is the number of buses allocated for hotplug PCI express
|
|
bridges, for use by hotplugged child devices. The default is 32
|
|
buses.
|
|
|
|
config PCIEXP_HOTPLUG_MEM
|
|
hex "PCI Express Hotplug Memory"
|
|
default 0x800000
|
|
help
|
|
This is the amount of memory space, in bytes, to allocate to
|
|
hotplug PCI express bridges, for use by hotplugged child devices.
|
|
This size should be page-aligned. The default is 8 MiB.
|
|
|
|
config PCIEXP_HOTPLUG_PREFETCH_MEM
|
|
hex "PCI Express Hotplug Prefetch Memory"
|
|
default 0x10000000
|
|
help
|
|
This is the amount of pre-fetchable memory space, in bytes, to
|
|
allocate to hot-plug PCI express bridges, for use by hotplugged
|
|
child devices. This size should be page-aligned. The default is
|
|
256 MiB.
|
|
|
|
config PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G
|
|
bool
|
|
default y if !PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
|
|
default n
|
|
help
|
|
This enables prefetch memory allocation above 4G boundary for the
|
|
hotplug resources.
|
|
|
|
config PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
|
|
bool "PCI Express Hotplug Prefetch Memory Allocation below 4G boundary"
|
|
default n
|
|
help
|
|
This enables prefetch memory allocation below 4G boundary for the
|
|
hotplug resources.
|
|
|
|
config PCIEXP_HOTPLUG_IO
|
|
hex "PCI Express Hotplug I/O Space"
|
|
default 0x2000
|
|
help
|
|
This is the amount of I/O space to allocate to hot-plug PCI
|
|
express bridges, for use by hotplugged child devices. The default
|
|
is 8 KiB.
|
|
|
|
endif # PCIEXP_HOTPLUG
|
|
|
|
endif # PCIEXP_PLUGIN_SUPPORT
|
|
|
|
config EARLY_PCI_BRIDGE
|
|
bool "Early PCI bridge"
|
|
depends on PCI
|
|
default n
|
|
help
|
|
While coreboot is executing code from ROM, the coreboot resource
|
|
allocator has not been running yet. Hence PCI devices living behind
|
|
a bridge are not yet visible to the system.
|
|
|
|
This option enables static configuration for a single pre-defined
|
|
PCI bridge function on bus 0.
|
|
|
|
if EARLY_PCI_BRIDGE
|
|
|
|
config EARLY_PCI_BRIDGE_DEVICE
|
|
hex "bridge device"
|
|
default 0x0
|
|
|
|
config EARLY_PCI_BRIDGE_FUNCTION
|
|
hex "bridge function"
|
|
default 0x0
|
|
|
|
config EARLY_PCI_MMIO_BASE
|
|
hex "MMIO window base"
|
|
default 0x0
|
|
|
|
endif # EARLY_PCI_BRIDGE
|
|
|
|
config SUBSYSTEM_VENDOR_ID
|
|
hex "Override PCI Subsystem Vendor ID"
|
|
depends on PCI
|
|
default 0x0000
|
|
help
|
|
This config option will override the devicetree settings for
|
|
PCI Subsystem Vendor ID.
|
|
|
|
Note: This option is not meant for a board's Kconfig; use the
|
|
devicetree setting `subsystemid` instead.
|
|
|
|
config SUBSYSTEM_DEVICE_ID
|
|
hex "Override PCI Subsystem Device ID"
|
|
depends on PCI
|
|
default 0x0000
|
|
help
|
|
This config option will override the devicetree settings for
|
|
PCI Subsystem Device ID.
|
|
|
|
Note: This option is not meant for a board's Kconfig; use the
|
|
devicetree setting `subsystemid` instead.
|
|
|
|
config VGA_BIOS
|
|
bool "Add a VGA BIOS image"
|
|
depends on ARCH_X86
|
|
select VGA_ROM_RUN_DEFAULT
|
|
help
|
|
Select this option if you have a VGA BIOS image that you would
|
|
like to add to your ROM.
|
|
|
|
You will be able to specify the location and file name of the
|
|
image later.
|
|
|
|
config VGA_BIOS_FILE
|
|
string "VGA BIOS path and filename"
|
|
depends on VGA_BIOS
|
|
default "vgabios.bin"
|
|
help
|
|
The path and filename of the file to use as VGA BIOS.
|
|
|
|
config VGA_BIOS_ID
|
|
string "VGA device PCI IDs"
|
|
depends on VGA_BIOS
|
|
default "1106,3230"
|
|
help
|
|
The comma-separated PCI vendor and device ID with optional revision if that
|
|
feature is enabled that would associate your vBIOS to your video card.
|
|
|
|
Example: 1106,3230 or 1106,3230,a3
|
|
|
|
In the above example 1106 is the PCI vendor ID (in hex, but without
|
|
the "0x" prefix) and 3230 specifies the PCI device ID of the
|
|
video card (also in hex, without "0x" prefix). a3 specifies the revision.
|
|
|
|
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
|
|
|
|
config VGA_BIOS_SECOND
|
|
bool "Add a 2nd video BIOS image"
|
|
depends on ARCH_X86 && VGA_BIOS
|
|
help
|
|
Select this option if you have a 2nd video BIOS image that you would
|
|
like to add to your ROM.
|
|
|
|
config VGA_BIOS_SECOND_FILE
|
|
string "2nd video BIOS path and filename"
|
|
depends on VGA_BIOS_SECOND
|
|
default "vbios2.bin"
|
|
help
|
|
The path and filename of the file to use as video BIOS.
|
|
|
|
config VGA_BIOS_SECOND_ID
|
|
string "Graphics device PCI IDs"
|
|
depends on VGA_BIOS_SECOND
|
|
help
|
|
The comma-separated PCI vendor and device ID with optional revision if that
|
|
feature is enabled that would associate your vBIOS to your video card.
|
|
|
|
Example: 1106,3230 or 1106,3230,a3
|
|
|
|
In the above example 1106 is the PCI vendor ID (in hex, but without
|
|
the "0x" prefix) and 3230 specifies the PCI device ID of the
|
|
video card (also in hex, without "0x" prefix). a3 specifies the revision.
|
|
|
|
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
|
|
|
|
config CHECK_REV_IN_OPROM_NAME
|
|
def_bool n
|
|
help
|
|
Select this in the platform BIOS or chipset if the option rom has a revision
|
|
that needs to be checked when searching CBFS.
|
|
|
|
config VGA_BIOS_DGPU
|
|
bool "Add a discrete VGA BIOS image"
|
|
depends on VGA_BIOS
|
|
help
|
|
Select this option if you have a VGA BIOS image for discrete GPU
|
|
that you would like to add to your ROM.
|
|
|
|
You will be able to specify the location and file name of the
|
|
image later.
|
|
|
|
config VGA_BIOS_DGPU_FILE
|
|
string "Discrete VGA BIOS path and filename"
|
|
depends on VGA_BIOS_DGPU
|
|
default "vgabios_dgpu.bin"
|
|
help
|
|
The path and filename of the file to use as VGA BIOS for discrete GPU.
|
|
|
|
config VGA_BIOS_DGPU_ID
|
|
string "Discrete VGA device PCI IDs"
|
|
depends on VGA_BIOS_DGPU
|
|
default "1002,6663"
|
|
help
|
|
The comma-separated PCI vendor and device ID that would associate
|
|
your VGA BIOS to your discrete video card.
|
|
|
|
Examples:
|
|
1002,6663 for HD 8570M
|
|
1002,6665 for R5 M230
|
|
|
|
In the above examples 1002 is the PCI vendor ID (in hex, but without
|
|
the "0x" prefix) and 6663 / 6665 specifies the PCI device ID of the
|
|
discrete video card (also in hex, without "0x" prefix).
|
|
|
|
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
|
|
|
|
config INTEL_GMA_HAVE_VBT
|
|
bool
|
|
help
|
|
Select this in the mainboard Kconfig to indicate the board has
|
|
a data.vbt file.
|
|
|
|
config INTEL_GMA_ADD_VBT
|
|
depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON
|
|
bool "Add a Video BIOS Table (VBT) binary to CBFS"
|
|
default y if INTEL_GMA_HAVE_VBT
|
|
help
|
|
Add a VBT data file to CBFS. The VBT describes the integrated
|
|
GPU and connections, and is needed by the GOP driver integrated into
|
|
FSP and the OS driver in order to initialize the display.
|
|
|
|
config INTEL_GMA_VBT_FILE
|
|
string "VBT binary path and filename"
|
|
depends on INTEL_GMA_ADD_VBT
|
|
default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(VARIANT_DIR)/data.vbt" \
|
|
if INTEL_GMA_HAVE_VBT && VARIANT_DIR != ""
|
|
default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" if INTEL_GMA_HAVE_VBT
|
|
default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/vbt.bin"
|
|
help
|
|
The path and filename of the VBT binary.
|
|
|
|
config SOFTWARE_I2C
|
|
bool "Enable I2C controller emulation in software"
|
|
default n
|
|
help
|
|
This config option will enable code to override the i2c_transfer
|
|
routine with a (simple) software emulation of the protocol. This may
|
|
be useful for debugging or on platforms where a driver for the real
|
|
I2C controller is not (yet) available. The platform code needs to
|
|
provide bindings to manually toggle I2C lines.
|
|
|
|
config I2C_TRANSFER_TIMEOUT_US
|
|
int "I2C transfer timeout in microseconds"
|
|
default 500000
|
|
help
|
|
Timeout for a read/write transfers on the I2C bus, that is, the
|
|
maximum time a device could stretch clock bits before the transfer
|
|
is aborted and an error returned.
|
|
|
|
config RESOURCE_ALLOCATION_TOP_DOWN
|
|
bool "Allocate resources from top down"
|
|
default n
|
|
help
|
|
Should be the default, but many platforms don't report resources
|
|
correctly. Hence, the allocator might cause conflicts.
|
|
|
|
config XHCI_UTILS
|
|
def_bool n
|
|
help
|
|
Provides xHCI utility functions.
|
|
|
|
source "src/device/dram/Kconfig"
|
|
|
|
endmenu
|