20cb85fa98
Add some known good values for some thinkpads displays. Known good means that at this pwm frequency the display is evenly lit on all duty cycles, the display makes minimal to no noise at lower duty cycles and the display does not flicker. This values differs from vendor (which uses an obviously wrong display clock (190MHz instead of 320MHz) resulting in frequency more than 60% off the intended value. TESTED on Thinkpad X200 with edid ascii string in list and removed from list to see if notice message is shown. Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* 2012 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H
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#define NORTHBRIDGE_INTEL_GM45_CHIP_H
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#include <drivers/intel/gma/i915.h>
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struct northbridge_intel_gm45_config {
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u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
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u16 gpu_panel_power_down_delay; /* T3 time sequence */
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u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
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u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
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u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
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struct i915_gpu_controller_info gfx;
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u16 default_pwm_freq;
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u8 duty_cycle;
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/*
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* Maximum PCI mmio size in MiB.
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*/
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u16 pci_mmio_size;
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};
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#endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */
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