e8ffa9ffd3
Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's SMM configuration. Once the BootDone command is sent, the PSP only responds to commands where the buffer is in SMM memory. Set aside a region for the core-to-PSP command buffer and the PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read as non-zero during an SMI. Add calls to soc functions for the soc to populate the trigger info and register info (v2 only). Add functions to set up the structures needed for the SmmInfo function in Picasso support. Issue a SW SMI, and add a new handler to call the new PSP function. BUG=b:153677737 Change-Id: I10088a53e786db788740e4b388650641339dae75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <soc/smi.h>
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#include <amdblocks/acpimmio_map.h>
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#include <amdblocks/psp.h>
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#define PSP_MAILBOX_OFFSET 0x10570
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#define MSR_CU_CBBCFG 0xc00110a2
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void *soc_get_mbox_address(void)
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{
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uintptr_t psp_mmio;
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psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
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if (psp_mmio == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: MSR_CU_CBBCFG uninitialized\n");
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return 0;
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}
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return (void *)(psp_mmio + PSP_MAILBOX_OFFSET);
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}
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void soc_fill_smm_trig_info(struct smm_trigger_info *trig)
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{
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if (!trig)
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return;
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trig->address = 0xfed802a8;
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trig->address_type = SMM_TRIGGER_MEM;
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trig->value_width = SMM_TRIGGER_DWORD;
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trig->value_and_mask = 0xfdffffff;
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trig->value_or_mask = 0x02000000;
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}
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void soc_fill_smm_reg_info(struct smm_register_info *reg)
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{
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if (!reg)
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return;
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reg->smi_enb.address = ACPIMMIO_SMI_BASE + SMI_REG_SMITRIG0;
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reg->smi_enb.address_type = SMM_TRIGGER_MEM;
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reg->smi_enb.value_width = SMM_TRIGGER_DWORD;
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reg->smi_enb.reg_bit_mask = SMITRG0_SMIENB;
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reg->smi_enb.expect_value = 0;
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reg->eos.address = ACPIMMIO_SMI_BASE + SMI_REG_SMITRIG0;
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reg->eos.address_type = SMM_TRIGGER_MEM;
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reg->eos.value_width = SMM_TRIGGER_DWORD;
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reg->eos.reg_bit_mask = SMITRG0_EOS;
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reg->eos.expect_value = SMITRG0_EOS;
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reg->psp_smi_en.address = ACPIMMIO_SMI_BASE + SMI_REG_CONTROL0;
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reg->psp_smi_en.address += sizeof(uint32_t) * SMITYPE_PSP / 16;
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reg->psp_smi_en.address_type = SMM_TRIGGER_MEM;
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reg->psp_smi_en.value_width = SMM_TRIGGER_DWORD;
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reg->psp_smi_en.reg_bit_mask = SMI_MODE_MASK << (2 * SMITYPE_PSP % 16);
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reg->psp_smi_en.expect_value = SMI_MODE_SMI << (2 * SMITYPE_PSP % 16);
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}
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