coreboot-kgpe-d16/src
Vladimir Serbinenko 4aad743434 i82801gx: Enable upper CMOS in bootblock.
Otherwise checksum may not work correctly on early stages.

For compatibility with old bootblocks also enable it early in romstage.

Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7556
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-12-03 21:02:12 +01:00
..
arch Replace hlt with halt() 2014-12-02 10:25:55 +01:00
console Add UCB RISCV support for architecture, soc, and emulation mainboard.. 2014-12-01 19:06:43 +01:00
cpu AGESA: Trace execution with AGESA_EVENTLOG() 2014-12-03 08:11:03 +01:00
device device/dram/ddr3.c: Fix sizeof on array func param overflow 2014-11-08 07:09:34 +01:00
drivers SPI: Add vendor Atmel 2014-12-03 05:29:04 +01:00
ec Replace hlt with halt() 2014-12-02 10:25:55 +01:00
include Replace hlt() loops with halt() 2014-11-30 12:20:07 +01:00
lib gcc.c: Test for gcc, not for non-clang 2014-11-30 12:20:37 +01:00
mainboard i82801gx: Enable upper CMOS in bootblock. 2014-12-03 21:02:12 +01:00
northbridge i82801gx: Enable upper CMOS in bootblock. 2014-12-03 21:02:12 +01:00
soc Replace hlt with halt() 2014-12-02 10:25:55 +01:00
southbridge i82801gx: Enable upper CMOS in bootblock. 2014-12-03 21:02:12 +01:00
superio Mark non-executable files non-executable 2014-12-01 17:33:07 +01:00
vendorcode Mark non-executable files non-executable 2014-12-01 17:33:07 +01:00
Kconfig Add UCB RISCV support for architecture, soc, and emulation mainboard.. 2014-12-01 19:06:43 +01:00