8d5b674739
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
135 lines
5.1 KiB
Text
135 lines
5.1 KiB
Text
chip soc/intel/braswell
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############################################################
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# Set the parameters for MemoryInit
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############################################################
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register "PcdMrcInitSpdAddr1" = "0xa0"
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register "PcdMrcInitSpdAddr2" = "0xa2"
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register "PcdIgdDvmt50PreAlloc" = "1"
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register "PcdDvfsEnable" = "0"
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register "PcdCaMirrorEn" = "1"
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############################################################
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# Set the parameters for SiliconInit
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############################################################
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register "PcdSdcardMode" = "PCH_ACPI_MODE"
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register "PcdEnableHsuart0" = "0"
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register "PcdEnableHsuart1" = "1"
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register "PcdEnableAzalia" = "1"
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register "PcdEnableXhci" = "1"
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register "PcdEnableLpe" = "1"
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register "PcdEnableDma0" = "1"
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register "PcdEnableDma1" = "1"
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register "PcdEnableI2C0" = "1"
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register "PcdEnableI2C1" = "1"
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register "PcdEnableI2C2" = "0"
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register "PcdEnableI2C3" = "0"
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register "PcdEnableI2C4" = "1"
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register "PcdEnableI2C5" = "1"
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register "PcdEnableI2C6" = "0"
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register "PunitPwrConfigDisable" = "0" # Enable SVID
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register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
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register "PcdEmmcMode" = "PCH_ACPI_MODE"
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register "PcdEnableSata" = "0" # Disable SATA
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register "Usb2Port0PerPortPeTxiSet" = "7"
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register "Usb2Port0PerPortTxiSet" = "5"
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register "Usb2Port0IUsbTxEmphasisEn" = "2"
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register "Usb2Port0PerPortTxPeHalf" = "1"
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register "Usb2Port1PerPortPeTxiSet" = "7"
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register "Usb2Port1PerPortTxiSet" = "3"
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register "Usb2Port1IUsbTxEmphasisEn" = "2"
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register "Usb2Port1PerPortTxPeHalf" = "1"
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register "Usb2Port2PerPortPeTxiSet" = "7"
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register "Usb2Port2PerPortTxiSet" = "3"
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register "Usb2Port2IUsbTxEmphasisEn" = "2"
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register "Usb2Port2PerPortTxPeHalf" = "1"
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register "Usb2Port3PerPortPeTxiSet" = "7"
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register "Usb2Port3PerPortTxiSet" = "3"
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register "Usb2Port3IUsbTxEmphasisEn" = "2"
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register "Usb2Port3PerPortTxPeHalf" = "1"
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register "Usb2Port4PerPortPeTxiSet" = "7"
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register "Usb2Port4PerPortTxiSet" = "3"
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register "Usb2Port4IUsbTxEmphasisEn" = "2"
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register "Usb2Port4PerPortTxPeHalf" = "1"
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register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"
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register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
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register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
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register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
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register "PcdPchSsicEnable" = "1"
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register "PMIC_I2CBus" = "0"
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register "ISPEnable" = "0" # Disable IUNIT
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register "ISPPciDevConfig" = "3"
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register "PcdSdDetectChk" = "0" # Disable SD card detect
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# LPE audio codec settings
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register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
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register "dptf_enable" = "true"
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# Enable devices in ACPI mode
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register "lpss_acpi_mode" = "1"
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register "emmc_acpi_mode" = "1"
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register "sd_acpi_mode" = "1"
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register "lpe_acpi_mode" = "1"
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# Disable SLP_X stretching after SUS power well fail.
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register "disable_slp_x_stretch_sus_fail" = "1"
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# Allow PCIe devices to wake system from suspend
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register "pcie_wake_enable" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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# EDS Table 24-4, Figure 24-5
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device pci 00.0 on end # 8086 2280 - SoC transaction router
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device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
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device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
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device pci 0b.0 on end # 8086 22dc - ?
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device pci 10.0 on end # 8086 2294 - MMC Port
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device pci 11.0 off end # 8086 0F15 - SDIO Port
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device pci 12.0 on end # 8086 0F16 - SD Port
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device pci 13.0 off end # 8086 22a3 - Sata controller
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device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time
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device pci 15.0 on end # 8086 22a8 - LP Engine Audio
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device pci 16.0 off end # 8086 22b7 - USB device
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device pci 18.0 on end # 8086 22c0 - SIO - DMA
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device pci 18.1 on end # 8086 22c1 - I2C Port 1
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device pci 18.2 on end # 8086 22c2 - I2C Port 2
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device pci 18.3 off end # 8086 22c3 - I2C Port 3
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device pci 18.4 off end # 8086 22c4 - I2C Port 4
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device pci 18.5 on end # 8086 22c5 - I2C Port 5
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device pci 18.6 on end # 8086 22c6 - I2C Port 6
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device pci 18.7 off end # 8086 22c7 - I2C Port 7
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device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine
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device pci 1b.0 on end # 8086 0F04 - HD Audio
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device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1
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device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2
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device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3
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device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4
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device pci 1e.0 on end # 8086 2286 - SIO - DMA
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device pci 1e.1 off end # 8086 0F08 - PWM 1
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device pci 1e.2 off end # 8086 0F09 - PWM 2
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device pci 1e.3 on end # 8086 228a - HSUART 1
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device pci 1e.4 off end # 8086 228c - HSUART 2
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device pci 1e.5 on end # 8086 228e - SPI 1
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device pci 1e.6 off end # 8086 2290 - SPI 2
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device pci 1e.7 off end # 8086 22ac - SPI 3
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device pci 1f.0 on # 8086 229c - LPC bridge
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chip drivers/pc80/tpm
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# Rising edge interrupt
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register "irq_polarity" = "2"
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device pnp 0c31.0 on
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irq 0x70 = 10
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end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC Bridge
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device pci 1f.3 off end # 8086 0F12 - SMBus 0
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end
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end
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