coreboot-kgpe-d16/src/soc/imgtec/pistachio
Aaron Durbin e5bad5cd3d verstage: use common program.ld for linking
There's no reason to have a separate verstage.ld now
that there is a unified stage linking strategy. Moreover
verstage support is throughout the code base as it is
so bring in those link script macros into the common
memlayout.h as that removes one more specific thing a
board/chipset needs to do in order to turn on verstage.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=None

Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11516
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-09 19:35:20 +00:00
..
include/soc verstage: use common program.ld for linking 2015-09-09 19:35:20 +00:00
bootblock.c pistachio: sort included header files 2015-06-10 22:21:55 +02:00
cbmem.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
clocks.c pistachio: sort included header files 2015-06-10 22:21:55 +02:00
ddr2_init.c pistachio: add DDR3 initialization code 2015-06-12 20:19:42 +02:00
ddr3_init.c Remove address from GPLv2 headers 2015-06-24 07:09:24 +02:00
Kconfig Remove old HAVE_UART_MEMORY_MAPPED select statements 2015-06-21 00:20:17 +02:00
Makefile.inc pistachio: add DDR3 initialization code 2015-06-12 20:19:42 +02:00
monotonic_timer.c imgtec/pistachio: remove timestamp_get() implementation 2015-08-31 13:55:13 +00:00
romstage.c pistachio: sort included header files 2015-06-10 22:21:55 +02:00
soc.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
spi.c pistachio: sort included header files 2015-06-10 22:21:55 +02:00
uart.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00