4c2245eb67
This patch does two things which will take effect in follow-up patches: 1. Add an intermediate Makefile rule for dd'ing BL1 into the coreboot.rom pre-image. This is modeled after a similar hack for the bd82x6x southbridge. 2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to pass the bootblock offset into cbfstool. Change-Id: I89da255dc903c387b754b06a11bb3439035ead87 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2093 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
42 lines
1.2 KiB
Makefile
42 lines
1.2 KiB
Makefile
# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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INTERMEDIATE += exynos5250_add_bl1
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romstage-y += clock.c
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romstage-y += clock_init.c
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romstage-y += exynos_cache.c
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romstage-y += lowlevel_init.S
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romstage-y += lowlevel_init_c.c
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romstage-y += pinmux.c
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romstage-y += power.c
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romstage-y += soc.c
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romstage-y += uart.c
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#ramstage-y += clock.c
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#ramstage-y += clock_init.c
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#ramstage-y += power.c
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#ramstage-y += uart.c
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##ramstage-y += spl.c
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#ramstage-y += pinmux.c
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##ramstage-y += tzpc_init.c
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ramstage-y += clock.c
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ramstage-y += clock_init.c
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ramstage-y += exynos_cache.c
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ramstage-y += lowlevel_init.S
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ramstage-y += lowlevel_init_c.c
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ramstage-y += pinmux.c
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ramstage-y += power.c
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ramstage-y += soc.c
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ramstage-y += uart.c
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#ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c
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#ramstage-$(CONFIG_SATA_AHCI) += sata.c
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ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c
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ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c
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ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c
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exynos5250_add_bl1: $(obj)/coreboot.pre
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printf " DD Adding Samsung Exynos5250 BL1\n"
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dd if=3rdparty/cpu/samsung/exynos5250/E5250.nbl1.bin \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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