Arthur Heymans 4c4f56a6ba nb/x4x/nortbridge.c: Compute TSEG resource allocation dynamically ... Computes TSEG size dynamically. Changes the size of legacy hole to match other Intel northbirdges. Refactor this a little by needing one less variable. Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>		2017-05-09 12:56:41 +02:00
..
acpi
arch	arch/x86: Share storage data structures between early stages	2017-05-01 17:37:59 +02:00
commonlib	commonlib: Add ID for STORAGE_DATA	2017-04-28 19:56:11 +02:00
console	console: rework log level to not be reliant on ROMSTAGE_CONST	2017-04-25 18:13:56 +02:00
cpu	nb/amd/amdk8: Link reset_test.c	2017-04-28 17:17:40 +02:00
device	lib/edid.c: Allow use of when not NGI	2017-05-03 16:16:32 +02:00
drivers	drivers/intel/wifi: provide weak get_wifi_sar_limits()	2017-05-08 06:09:56 +02:00
ec	ec/google/chromeec: provide reboot function	2017-05-05 23:23:58 +02:00
include	drivers/spi: Re-factor spi_crop_chunk	2017-05-05 23:42:19 +02:00
lib	lib/edid: Save the display ASCII string	2017-05-03 16:18:15 +02:00
mainboard	mainboard/intel/galileo: Add SD controller configuration	2017-05-08 19:14:12 +02:00
northbridge	nb/x4x/nortbridge.c: Compute TSEG resource allocation dynamically	2017-05-09 12:56:41 +02:00
soc	soc/intel/skylake: Enable MTRR check	2017-05-08 19:14:23 +02:00
southbridge	drivers/spi: Re-factor spi_crop_chunk	2017-05-05 23:42:19 +02:00
superio	superio/fintek: Add support for Fintek F71808A	2017-03-27 19:19:56 +02:00
vboot	vboot: Separate board name and version number in FWID with a dot	2017-04-29 01:44:10 +02:00
vendorcode	cr50: check if the new image needs to be enabled and act on it	2017-05-05 23:24:20 +02:00
Kconfig	cr50: check if the new image needs to be enabled and act on it	2017-05-05 23:24:20 +02:00