4c6dfbc2c1
Using common watchdog timer (WDT) code for reset. Set up watchdog timer in mtk_wdt_init() to get reset status and disable auto-reboot. Link common do_hard_reset() to support hard reset. BUG=b:80501386 BRANCH=none TEST=both mtk_wdt_init() and do_hard_reset() work on Kukui. Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
37 lines
1.2 KiB
Makefile
37 lines
1.2 KiB
Makefile
ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
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bootblock-$(CONFIG_SPI_FLASH) += spi.c
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bootblock-y += ../common/timer.c
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ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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endif
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bootblock-y += ../common/wdt.c
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verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
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verstage-$(CONFIG_SPI_FLASH) += spi.c
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verstage-y += ../common/timer.c
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verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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verstage-y += ../common/wdt.c
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romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
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romstage-$(CONFIG_SPI_FLASH) += spi.c
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romstage-y += ../common/timer.c
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romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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romstage-y += ../common/wdt.c
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ramstage-y += ../common/cbmem.c emi.c
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ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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ramstage-y += ../common/timer.c
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ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
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ramstage-y += ../common/wdt.c
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CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
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CPPFLAGS_common += -Isrc/soc/mediatek/common/include
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$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
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./util/mtkheader/gen-bl-img.py mt8183 emmc $< $@
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endif
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