d4d5e4d3e1
The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/435 Tested-by: build bot (Jenkins)
12 lines
176 B
Text
12 lines
176 B
Text
config CPU_VIA_C3
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bool
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if CPU_VIA_C3
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select UDELAY_TSC
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select MMX
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select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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endif # CPU_VIA_C3
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