37765930ec
For pq module size registers such as DISP_AAL_SIZE, the high bits should be HSIZE, while low bits should be VSIZE. Fix the incorrect settings for these registers where width and height are reversed. According to MediaTek, there is no practical impact on mt8183 devices, but it's still nice to get this fixed to avoid future confusion. BUG=b:171167210 TEST=none BRANCH=kukui Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46626 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
88 lines
2.4 KiB
C
88 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <edid.h>
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#include <soc/addressmap.h>
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#include <soc/ddp.h>
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#include <types.h>
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static void disp_config_main_path_connection(void)
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{
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write32(&mmsys_cfg->disp_ovl0_mout_en, OVL0_MOUT_EN_OVL0_2L);
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write32(&mmsys_cfg->disp_ovl0_2l_mout_en, OVL0_2L_MOUT_EN_DISP_PATH0);
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write32(&mmsys_cfg->disp_path0_sel_in, DISP_PATH0_SEL_IN_OVL0_2L);
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write32(&mmsys_cfg->disp_rdma0_sout_sel_in, RDMA0_SOUT_SEL_IN_COLOR);
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write32(&mmsys_cfg->disp_dither0_mout_en, DITHER0_MOUT_EN_DISP_DSI0);
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write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0_MOUT);
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}
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static void disp_config_main_path_mutex(void)
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{
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write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
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/* Clock source from DSI0 */
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write32(&disp_mutex->mutex[0].ctl,
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MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
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write32(&disp_mutex->mutex[0].en, BIT(0));
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}
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static void ovl_bgclr_in_sel(u32 idx)
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{
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setbits32(&disp_ovl[idx]->datapath_con, BIT(2));
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}
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static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height,
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int enable_relay)
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{
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write32(®s->size, width << 16 | height);
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if (enable_relay)
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write32(®s->cfg, PQ_RELAY_MODE);
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write32(®s->en, PQ_EN);
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}
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static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
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{
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u32 idx = 0;
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u32 pixel_clk = width * height * vrefresh;
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for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++)
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ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff);
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rdma_config(width, height, pixel_clk, 5 * KiB);
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color_start(width, height);
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enable_pq(disp_ccorr, width, height, 1);
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enable_pq(disp_aal, width, height, 0);
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enable_pq(disp_gamma, width, height, 0);
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enable_pq(disp_dither, width, height, 1);
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disp_config_main_path_connection();
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disp_config_main_path_mutex();
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}
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static void disp_clock_on(void)
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{
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clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
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clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
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CG_CON1_DISP_DSI0_INTERFACE);
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}
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void mtk_ddp_init(void)
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{
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disp_clock_on();
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/* Turn off M4U port. */
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write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0);
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}
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void mtk_ddp_mode_set(const struct edid *edid)
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{
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u32 fmt = OVL_INFMT_RGBA8888;
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u32 bpp = edid->framebuffer_bits_per_pixel / 8;
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u32 width = edid->mode.ha;
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u32 height = edid->mode.va;
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u32 vrefresh = edid->mode.refresh;
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main_disp_path_setup(width, height, vrefresh);
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rdma_start();
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ovl_layer_config(fmt, bpp, width, height);
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ovl_bgclr_in_sel(1);
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}
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