Angel Pons 20a9533946 sb/intel/bd82x6x: Rework PCH ID cache ... Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore. Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>		2024-01-18 04:38:56 +00:00
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amd	sb/amd/pi/hudson/Kconfig: replace HUDSON_LEGACY_FREE option	2024-01-12 00:36:47 +00:00
intel	sb/intel/bd82x6x: Rework PCH ID cache	2024-01-18 04:38:56 +00:00
ricoh/rl5c476	commonlib,console,nb,sb,security: Add SPDX licenses to Makefiles	2023-08-14 15:14:45 +00:00
ti	commonlib,console,nb,sb,security: Add SPDX licenses to Makefiles	2023-08-14 15:14:45 +00:00