a46a712610
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
153 lines
4.4 KiB
C
153 lines
4.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <southbridge/amd/sb600/sb600.h>
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#define ADT7461_ADDRESS 0x4C
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#define ARA_ADDRESS 0x0C /* Alert Response Address */
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#define SMBUS_IO_BASE 0x1000
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extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
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extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
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u8 val);
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#define ADT7461_read_byte(address) \
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do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
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#define ARA_read_byte(address) \
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do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
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#define ADT7461_write_byte(address, val) \
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do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
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/***************************************************
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* This board, the TIM-8690 has two Marvel 88e5056 PCI-E
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* 10/100/1000 chips on board.
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* Both of their pin PERSTn pins are connected to GPIO 5 of the
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* SB600 southbridge.
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****************************************************/
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static void enable_onboard_nic(void)
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{
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u8 byte;
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device_t sm_dev;
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printk(BIOS_INFO, "enable_onboard_nic.\n");
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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byte = pci_read_config8(sm_dev, 0x9a);
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byte |= ( 1 << 7);
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pci_write_config8(sm_dev, 0x9a, byte);
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byte=pm_ioread(0x59);
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byte &= ~( 1<< 5);
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pm_iowrite(0x59,byte);
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byte = pci_read_config8(sm_dev, 0xA8);
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byte |= (1 << 1); //set bit 1 to high
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pci_write_config8(sm_dev, 0xA8, byte);
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}
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/* set thermal config
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*/
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static void set_thermal_config(void)
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{
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u8 byte;
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u16 word;
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device_t sm_dev;
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/* set ADT 7461 */
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ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
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ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
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ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
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ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
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ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
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ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
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byte = ADT7461_read_byte(0x02); /* read status register to clear it */
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ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
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printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
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/* sb600 settings for thermal config */
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/* set SB600 GPIO 64 to GPIO with pull-up */
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byte = pm2_ioread(0x42);
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byte &= 0x3f;
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pm2_iowrite(0x42, byte);
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/* set GPIO 64 to input */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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word = pci_read_config16(sm_dev, 0x56);
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word |= 1 << 7;
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pci_write_config16(sm_dev, 0x56, word);
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/* set GPIO 64 internal pull-up */
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byte = pm2_ioread(0xf0);
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byte &= 0xee;
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pm2_iowrite(0xf0, byte);
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/* set Talert to be active low */
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byte = pm_ioread(0x67);
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byte &= ~(1 << 5);
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pm_iowrite(0x67, byte);
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/* set Talert to generate ACPI event */
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byte = pm_ioread(0x3c);
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byte &= 0xf3;
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pm_iowrite(0x3c, byte);
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/* THERMTRIP pin */
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/* byte = pm_ioread(0x68);
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* byte |= 1 << 3;
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* pm_iowrite(0x68, byte);
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*
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* byte = pm_ioread(0x55);
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* byte |= 1 << 0;
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* pm_iowrite(0x55, byte);
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*
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* byte = pm_ioread(0x67);
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* byte &= ~( 1 << 6);
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* pm_iowrite(0x67, byte);
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*/
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}
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/*************************************************
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* enable the dedicated function in tim8690 board.
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* This function called early than rs690_enable.
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*************************************************/
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static void mainboard_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
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enable_onboard_nic();
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set_thermal_config();
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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