4d6ad838e7
This is an nvidia t210 based board. This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10635 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
231 lines
6 KiB
C
231 lines
6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <arch/io.h>
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#include <arch/mmu.h>
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#include <boot/coreboot_tables.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <soc/addressmap.h>
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#include <soc/clk_rst.h>
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#include <soc/clock.h>
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#include <soc/funitcfg.h>
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#include <soc/padconfig.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/nvidia/tegra/pingroup.h>
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#include <soc/nvidia/tegra/dc.h>
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#include <soc/display.h>
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#include <soc/mtc.h>
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#include <soc/pmc.h>
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#include <soc/power.h>
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#if IS_ENABLED(CONFIG_CHROMEOS)
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#include <vendorcode/google/chromeos/vboot_handoff.h>
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#include <vendorcode/google/chromeos/vboot2/misc.h>
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#endif
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#include <delay.h>
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#include "gpio.h"
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#include "pmic.h"
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static const struct pad_config padcfgs[] = {
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PAD_CFG_GPIO_INPUT(USB_VBUS_EN1, PINMUX_PULL_NONE | PINMUX_PARKED |
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PINMUX_INPUT_ENABLE | PINMUX_LPDR | PINMUX_IO_HV),
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};
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static const struct pad_config audio_codec_pads[] = {
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/* GPIO_X1_AUD(BB3) is CODEC_RST_L and DMIC1_DAT(E1) is AUDIO_ENABLE */
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PAD_CFG_GPIO_OUT1(GPIO_X1_AUD, PINMUX_PULL_DOWN),
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PAD_CFG_GPIO_OUT1(DMIC1_DAT, PINMUX_PULL_DOWN),
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};
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static const struct pad_config i2s1_pad[] = {
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/* I2S1 */
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PAD_CFG_SFIO(DAP1_SCLK, PINMUX_INPUT_ENABLE, I2S1),
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PAD_CFG_SFIO(DAP1_FS, PINMUX_INPUT_ENABLE, I2S1),
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PAD_CFG_SFIO(DAP1_DOUT, PINMUX_INPUT_ENABLE, I2S1),
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PAD_CFG_SFIO(DAP1_DIN, PINMUX_INPUT_ENABLE | PINMUX_TRISTATE, I2S1),
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/* codec MCLK via AUD SFIO */
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PAD_CFG_SFIO(AUD_MCLK, PINMUX_PULL_NONE, AUD),
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};
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static const struct funit_cfg audio_funit[] = {
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/* We need 1.5MHz for I2S1. So we use CLK_M */
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FUNIT_CFG(I2S1, CLK_M, 1500, i2s1_pad, ARRAY_SIZE(i2s1_pad)),
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};
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static const struct funit_cfg funits[] = {
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FUNIT_CFG_USB(USBD),
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FUNIT_CFG(SDMMC4, PLLP, 48000, NULL, 0),
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/* I2C6 for audio, temp sensor, etc. Enable codec via GPIOs/muxes */
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FUNIT_CFG(I2C6, PLLP, 400, audio_codec_pads, ARRAY_SIZE(audio_codec_pads)),
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};
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/* Audio init: clocks and enables/resets */
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static void setup_audio(void)
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{
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/* Audio codec (RT5677) uses 12MHz CLK1/EXTPERIPH1 */
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clock_configure_source(extperiph1, PLLP, 12000);
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/* Configure AUD_MCLK pad drive strength */
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write32((unsigned int *)TEGRA_APB_MISC_GP_BASE + 0xF4,
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(0x10 << PINGROUP_DRVUP_SHIFT | 0x10 << PINGROUP_DRVDN_SHIFT));
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/* Set up audio peripheral clocks/muxes */
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soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit));
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/* Enable CLK1_OUT */
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clock_external_output(1);
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/*
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* As per NVIDIA hardware team, we need to take ALL audio devices
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* connected to AHUB (AUDIO, APB2APE, I2S, SPDIF, etc.) out of reset
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* and clock-enabled, otherwise reading AHUB devices (in our case,
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* I2S/APBIF/AUDIO<XBAR>) will hang.
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*/
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soc_configure_ape();
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clock_enable_audio();
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}
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static const struct pad_config lcd_gpio_padcfgs[] = {
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/* LCD_EN */
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PAD_CFG_GPIO_OUT0(LCD_BL_EN, PINMUX_PULL_UP),
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/* LCD_RST_L */
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PAD_CFG_GPIO_OUT0(LCD_RST, PINMUX_PULL_UP),
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/* EN_VDD_LCD */
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PAD_CFG_GPIO_OUT0(LCD_GPIO2, PINMUX_PULL_NONE),
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/* EN_VDD18_LCD */
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PAD_CFG_GPIO_OUT0(LCD_GPIO1, PINMUX_PULL_NONE),
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};
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static void configure_display_clocks(void)
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{
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u32 lclks = CLK_L_HOST1X | CLK_L_DISP1; /* dc */
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u32 hclks = CLK_H_MIPI_CAL | CLK_H_DSI; /* mipi phy, mipi-dsi a */
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u32 uclks = CLK_U_DSIB; /* mipi-dsi b */
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u32 xclks = CLK_X_UART_FST_MIPI_CAL; /* uart_fst_mipi_cal */
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clock_enable_clear_reset(lclks, hclks, uclks, 0, 0, xclks, 0);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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/* CLK72MHZ_CLK_SRC */
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clock_configure_source(uart_fst_mipi_cal, PLLP_OUT3, 68000);
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}
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static int enable_lcd_vdd(void)
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{
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/* Set 1.20V to power AVDD_DSI_CSI */
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/* LD0: 1.20v CNF1: 0x0d */
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pmic_write_reg_77620(I2CPWR_BUS, MAX77620_CNFG1_L0_REG, 0xd0, 1);
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/* Enable VDD_LCD */
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gpio_set(EN_VDD_LCD, 1);
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/* wait for 2ms */
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mdelay(2);
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/* Enable PP1800_LCDIO to panel */
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gpio_set(EN_VDD18_LCD, 1);
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/* wait for 1ms */
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mdelay(1);
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/* Set panel EN and RST signals */
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gpio_set(LCD_EN, 1); /* enable */
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/* wait for min 10ms */
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mdelay(10);
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gpio_set(LCD_RST_L, 1); /* clear reset */
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/* wait for min 3ms */
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mdelay(3);
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return 0;
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}
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static int configure_display_blocks(void)
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{
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/* enable display related clocks */
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configure_display_clocks();
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/* configure panel gpio pads */
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soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
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/* set and enable panel related vdd */
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if (enable_lcd_vdd())
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return -1;
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return 0;
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}
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static void powergate_unused_partitions(void)
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{
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static const uint32_t partitions[] = {
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POWER_PARTID_PCX,
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POWER_PARTID_SAX,
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POWER_PARTID_NVDEC,
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POWER_PARTID_NVJPG,
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POWER_PARTID_DFD,
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};
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int i;
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for (i = 0; i < ARRAY_SIZE(partitions); i++)
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power_gate_partition(partitions[i]);
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}
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static void mainboard_init(device_t dev)
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{
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soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
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soc_configure_funits(funits, ARRAY_SIZE(funits));
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/* I2C6 bus (audio, etc.) */
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soc_configure_i2c6pad();
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i2c_init(I2C6_BUS);
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setup_audio();
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/* if panel needs to bringup */
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#if IS_ENABLED(CONFIG_CHROMEOS)
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if (!vboot_skip_display_init())
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#endif
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configure_display_blocks();
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powergate_unused_partitions();
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}
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void display_startup(device_t dev)
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{
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dsi_display_startup(dev);
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}
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static void mainboard_enable(device_t dev)
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{
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dev->ops->init = &mainboard_init;
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}
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struct chip_operations mainboard_ops = {
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.name = "smaug",
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.enable_dev = mainboard_enable,
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};
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void lb_board(struct lb_header *header)
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{
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#if IS_ENABLED(CONFIG_CHROMEOS)
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lb_table_add_serialno_from_vpd(header);
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#endif
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soc_add_mtc(header);
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}
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