8e63017096
A few things are currently missing: - The trap handler doesn't set the stack pointer, which can easily result in trap loops or memory corruptions. - The SBI trampolin page (as described in version 1.9 of the RISC-V Privileged Architecture Specification), has been removed for now. Change-Id: Id89c859fab354501c94a0e82d349349c29fa4cc6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15591 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
48 lines
1.1 KiB
ArmAsm
48 lines
1.1 KiB
ArmAsm
/*
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* Early initialization code for RISC-V
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*
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* Copyright 2013 Google Inc.
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* Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <arch/encoding.h>
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.section ".text._start", "ax", %progbits
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.globl _start
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_start:
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#define STACK_START 0x80800000 /* 2GiB + 8MiB */
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#define STACK_SIZE 0x0000fff0
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li sp, STACK_START + STACK_SIZE
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# make room for HLS and initialize it
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addi sp, sp, -64 // MENTRY_FRAME_SIZE
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csrr a0, mhartid
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call hls_init
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# poison the stack
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li t1, STACK_START
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li t0, 0xdeadbeef
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sd t0, 0(t1)
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la t0, trap_entry
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csrw mtvec, t0
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# clear any pending interrupts
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csrwi mip, 0
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# set up the mstatus register for VM
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call mstatus_init
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tail main
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