98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _RULES_H
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#define _RULES_H
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/* Useful helpers to tell whether the code is executing in bootblock,
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* romstage, ramstage or SMM.
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*/
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#if defined(__BOOTBLOCK__)
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#define ENV_BOOTBLOCK 1
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#elif defined(__ROMSTAGE__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 1
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#elif defined(__SMM__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 1
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#elif defined(__VERSTAGE__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 1
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#define ENV_RMODULE 0
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#elif defined(__RAMSTAGE__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 1
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#elif defined(__RMODULE__)
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 1
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#else
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/*
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* Default case of nothing set for random blob generation using
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* create_class_compiler that isn't bound to a stage. Also AGESA
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* apparently builds things compeletely separate from coreboot's
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* build infrastructure -- hardcoding its own rules.
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*/
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#define ENV_BOOTBLOCK 0
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#define ENV_ROMSTAGE 0
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#define ENV_RAMSTAGE 0
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#define ENV_SMM 0
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#define ENV_VERSTAGE 0
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#define ENV_RMODULE 0
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#endif
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/* For romstage and ramstage always build with simple device model, ie.
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* PCI, PNP and CPU functions operate without use of devicetree.
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*
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* For ramstage individual source file may define __SIMPLE_DEVICE__
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* before including any header files to force that particular source
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* be built with simple device model.
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*/
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#if defined(__PRE_RAM__) || defined(__SMM__)
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#define __SIMPLE_DEVICE__
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#endif
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#endif /* _RULES_H */
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