1d8b0979c3
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
49 lines
938 B
Text
49 lines
938 B
Text
source src/cpu/amd/Kconfig
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source src/cpu/emulation/Kconfig
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source src/cpu/intel/Kconfig
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source src/cpu/via/Kconfig
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source src/cpu/x86/Kconfig
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config USE_DCACHE_RAM
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bool
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default n
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config DCACHE_RAM_BASE
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hex
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default 0xffdf8000 if CPU_INTEL_CORE
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config DCACHE_RAM_SIZE
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hex
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default 0x8000 if CPU_INTEL_CORE
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x0
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config SMP
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bool
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default y if MAX_CPUS != 1
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default n
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help
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This option is used to enable certain functions to make coreboot
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work correctly on symmetric multi processor (SMP) systems.
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# Set MMX and SSE in socket or model if the CPU has them.
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# If all CPUs for the socket have MMX or SSE, set them there.
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# These options are only needed for boards compiled with romcc.
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config MMX
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bool
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config SSE
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bool
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config VAR_MTRR_HOLE
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bool
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default y
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help
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Unset this if you don't want the MTRR code to use
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subtractive MTRRs
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