1ae592b468
Add a common detect_s3_resume function. Will be used by other southbridge code. TODO: Merge with soc/intel/common/*/pmclib Tested on Lenovo T520 (Intel Sandy Bridge) with Change I283a841575430f2f179997db8d2f08fa3978a0bb applied as well. Still boots to OS, no errors visible in dmesg and S3 resume is working. Change-Id: I88023af522afac8164f068b0fbe0eac601aef702 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <arch/acpi.h>
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#include <console/console.h>
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#include "pmclib.h"
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#include "pmbase.h"
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#include "pmutil.h"
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int southbridge_detect_s3_resume(void)
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{
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u32 pm1_cnt;
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u16 pm1_sts;
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int is_s3 = 0;
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/* Check PM1_STS[15] to see if we are waking from Sx */
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pm1_sts = read_pmbase16(PM1_STS);
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if (pm1_sts & WAK_STS) {
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/* Read PM1_CNT[12:10] to determine which Sx state */
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pm1_cnt = read_pmbase32(PM1_CNT);
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if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) {
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/* Clear SLP_TYPE. */
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write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10));
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is_s3 = 1;
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}
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}
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if (is_s3) {
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if (!acpi_s3_resume_allowed()) {
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printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n");
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return 0;
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}
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printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n");
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}
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return is_s3;
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}
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