Furquan Shaikh edac4ef6d4 mb, soc/intel: Reorganize CNVi device entries in devicetree ... This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>		2020-11-02 06:15:06 +00:00
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spd	mb: remove duplicated Make code for spd.bin generation	2020-09-06 14:57:06 +00:00
variants	mb, soc/intel: Reorganize CNVi device entries in devicetree	2020-11-02 06:15:06 +00:00
board_info.txt
bootblock.c
chromeos.c
chromeos.fmd
dsdt.asl	{src/mb,util/autoport}: Use macro for DSDT revision	2020-10-13 18:27:04 +00:00
ec.c
hda_verb.c
Kconfig	treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFS	2020-09-23 09:00:47 +00:00
Kconfig.name
Makefile.inc
ramstage.c
romstage.c
smihandler.c