afa07f7ae4
This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.
BUG=b:78109109
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.
Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
63 lines
1.4 KiB
Text
63 lines
1.4 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2017 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if BOARD_INTEL_SKLSDLBRK
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BOARD_ROMSIZE_KB_4096
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select CONSOLE_SERIAL
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select DRIVERS_UART
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select GENERIC_SPD_BIN
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select SERIRQ_CONTINUOUS_MODE
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select SKYLAKE_SOC_PCH_H
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select SOC_INTEL_SKYLAKE
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select SUPERIO_NUVOTON_NCT6776
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select SUPERIO_NUVOTON_NCT6776_COM_A
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select SADDLEBROOK_USES_FSP1_1
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select HAVE_CMOS_DEFAULT
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config SADDLEBROOK_USES_FSP1_1
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bool "FSP driver 1.1"
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAINBOARD_DIR
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string
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default "intel/saddlebrook"
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config MAINBOARD_PART_NUMBER
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string
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default "Skylake Saddle Brook"
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config MAINBOARD_FAMILY
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string
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default "Intel_SaddleBrook"
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config MAX_CPUS
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int
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default 8
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config TPM_PIRQ
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hex
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default 0x18 # GPP_E0_IRQ
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endif
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