989e12bb63
ARM processors save the PC value in the Link Register when they handle and exception, but they store it with an added offset (depending on the exception type). In order to make crashes easier to read and correctly support more complicated handlers in libpayload, this patch adjusts the saved PC value on exception entry to correct for that offset. (Note: The value that we now store is what ARM calls the "preferred return address". For most exceptions this is the faulting instruction, but for software interrupts (SWI) it is the instruction after that. This is the way most programs like GDB expect the stored PC address to work, so let's leave it at that.) Numbers taken from the Architecture Reference Manual at the end of section B1.8.3. BRANCH=none BUG=chrome-os-partner:18390 TEST=Provoked a data abort and an undefined instruction in both coreboot and depthcharge, confirmed that the PC address was spot on. Original-Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199844 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 4a914d36bb181d090f75b1414158846d40dc9bac) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib63ca973d5f037a879b4d4d258a4983160b67dd6 Reviewed-on: http://review.coreboot.org/7992 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
122 lines
2.7 KiB
ArmAsm
122 lines
2.7 KiB
ArmAsm
/*
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* This file is part of the libpayload project.
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*
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* Copyright 2013 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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.text
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.align 6
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.arm
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.global exception_table
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exception_table:
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b 1f
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b 2f
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b 3f
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b 4f
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b 5f
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b 6f
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b 7f
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b 8f
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1:
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mov sp, $0
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b exception_common
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/* Undefined Instruction (CAREFUL: the PC offset is specific to thumb mode!) */
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2:
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sub lr, lr, $2
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mov sp, $1
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b exception_common
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/* Software Interrupt (no PC offset necessary) */
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3:
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mov sp, $2
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b exception_common
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/* Prefetch Abort */
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4:
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sub lr, lr, $4
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mov sp, $3
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b exception_common
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/* Data Abort */
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5:
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sub lr, lr, $8
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mov sp, $4
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b exception_common
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/* (not used) */
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6:
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mov sp, $5
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b exception_common
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/* Interrupt */
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7:
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sub lr, lr, $4
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mov sp, $6
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b exception_common
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/* Fast Interrupt */
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8:
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sub lr, lr, $4
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mov sp, $7
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b exception_common
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exception_common:
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str sp, exception_idx
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ldr sp, exception_stack_end
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push { lr }
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stmfd sp, { sp, lr }^
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sub sp, sp, $8
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push { r0 - r12 }
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mrs r0, SPSR
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push { r0 }
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mov r0, sp
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ldr r1, exception_idx
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blx exception_dispatch
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pop { r0 }
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msr SPSR_cxsf, r0
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pop { r0 - r12 }
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add sp, sp, $8
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ldmfd sp!, { pc }^
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.align 2
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.global exception_stack_end
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exception_stack_end:
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.word 0
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exception_idx:
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.word 0
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.thumb
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.global set_vbar
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.thumb_func
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set_vbar:
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mcr p15, 0, r0, c12, c0, 0
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bx lr
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