540a98001d
According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
154 lines
4.3 KiB
C
154 lines
4.3 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <libpayload.h>
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#include <assert.h>
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#include <die.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <arch/cache.h>
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#include <arch/virtual.h>
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#include <arch/io.h>
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unsigned long virtual_offset = 0;
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extern char _end[];
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/*
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* MAIR Index
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* (Originally defined in src/arch/arm/include/armv7/arch/cache.h)
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*/
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#define MAIR_INDX_NC 0
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#define MAIR_INDX_WT 1
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#define MAIR_INDX_WB 2
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/*
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* Translation Table Attribute
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* (Originally defined in src/arch/arm/include/armv7/arch/cache.h)
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*/
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#define ATTR_BASE (\
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0ULL << 54 | /* PN. 0:Not restricted */ \
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0ULL << 53 | /* PXN. 0:Not restricted */ \
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1 << 10 | /* AF. 1:Accessed. This is to prevent access \
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* fault when accessed for the first time */ \
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0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
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0 << 5 | /* NS. 0:Output address is in Secure space */ \
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0 << 1 | /* block/table. 0:block entry */ \
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1 << 0 /* validity. 1:valid */ \
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)
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#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2))
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#define ATTR_WT (ATTR_BASE | (MAIR_INDX_WT << 2))
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#define ATTR_WB (ATTR_BASE | (MAIR_INDX_WB << 2))
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/* Translation Table Entry */
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typedef uint64_t pmd_t;
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typedef uint64_t pgd_t;
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#define SECTION_SHIFT 30
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#define BLOCK_SHIFT 21
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#define PAGE_SHIFT 12
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#define PGD_MASK (~0 << PAGE_SHIFT)
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static pmd_t *ttb_buff = 0;
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static uintptr_t work_block;
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static pmd_t original_map;
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int getpagesize(void)
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{
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return 1 << PAGE_SHIFT;
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}
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static void lpae_map_init(void)
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{
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pgd_t *pgd;
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die_if(!(read_ttbcr() >> 31), "LPAE is not enabled\n");
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/* get work block address */
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work_block = ALIGN_UP((uintptr_t)_end, 2*MiB);
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assert(work_block);
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printf("Work block for LPAE mapping is @ %p\n", (void *)work_block);
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/* get the address of the 1st pmd from pgd[0] */
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pgd = (pgd_t *)((uintptr_t)read_ttbr0() & PGD_MASK);
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ttb_buff = (pmd_t *)((uintptr_t)pgd[0] & PGD_MASK);
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assert(ttb_buff);
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original_map = ttb_buff[work_block >> BLOCK_SHIFT];
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}
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static void lpae_flush_work_block(void)
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{
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dccmvac((uintptr_t)&ttb_buff[work_block >> BLOCK_SHIFT]);
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dsb();
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tlbimvaa(work_block);
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dsb();
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isb();
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}
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/**
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* Maps a 2MB designated block to a requested physical address, and returns
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* the address to the block or NULL on error.
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*
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* pa_mb: Physical address in MB. Has to be on a 2MB boundary.
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* policy: Data chache policy
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*/
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void *lpae_map_phys_addr(unsigned long pa_mb, enum dcache_policy policy)
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{
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pmd_t attr;
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if (!ttb_buff)
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lpae_map_init();
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switch(policy) {
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case DCACHE_OFF:
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attr = ATTR_NC;
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break;
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case DCACHE_WRITEBACK:
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attr = ATTR_WB;
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break;
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case DCACHE_WRITETHROUGH:
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attr = ATTR_WT;
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break;
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default:
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return NULL;
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}
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ttb_buff[work_block >> BLOCK_SHIFT] =
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((pmd_t)pa_mb/2 << BLOCK_SHIFT) | attr;
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lpae_flush_work_block();
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return (void *)work_block;
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}
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void lpae_restore_map(void)
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{
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ttb_buff[work_block >> BLOCK_SHIFT] = original_map;
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lpae_flush_work_block();
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}
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