coreboot-kgpe-d16/src
Aaron Durbin 50c3ba24d4 intel/skylake: unconditionally set SPI controller BAR
The setting of the SPI controller BAR was conditional
on the nominal frequency being set. Therefore, that doesn't
mean the SPI BAR is set on all boots. Move the setting of
the BAR in the southbridge_bootblock_init() which is called
prioer to cpu_bootblock_init().

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Confirmed spibar is always set on glados.

Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8
Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/319461
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13587
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 17:43:49 +01:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch xcompile: Add a way to specify -march=i586 2016-02-03 02:58:10 +01:00
commonlib commonlib: move uefi includes out of commonlib includes 2016-02-02 14:27:03 +01:00
console console: Simplify bootblock console Kconfig selection logic 2016-01-21 05:37:27 +01:00
cpu src: Fix various spelling and whitespace issues. 2016-02-02 14:37:09 +01:00
device arch/x86: Drop arch/pciconf.h 2016-01-26 20:22:44 +01:00
drivers soc/intel/common: Use SoC specific routine to read/write MTRRs 2016-02-02 19:00:35 +01:00
ec google/chromeec: implement vboot_(save|retrieve)_hash API 2016-02-04 17:34:58 +01:00
include include/device: Move inline functions from pci_def.h to pci.h 2016-02-03 03:32:58 +01:00
lib lib: add bootmode.c to verstage 2016-02-04 17:36:07 +01:00
mainboard google/lars: perform early init for CAR *stage 2016-02-04 17:42:20 +01:00
northbridge northbridge/intel/peg: Disable unused ports 2016-02-04 01:44:40 +01:00
soc intel/skylake: unconditionally set SPI controller BAR 2016-02-04 17:43:49 +01:00
southbridge drivers/pc80: Add PS/2 mouse presence detect 2016-02-01 22:10:46 +01:00
superio drivers/pc80: Add PS/2 mouse presence detect 2016-02-01 22:10:46 +01:00
vendorcode google/chromeos/vboot2: honor boot region device size 2016-02-04 17:42:54 +01:00
Kconfig chromeos/vboot: provide support for x86 memory init verification 2016-02-04 17:34:00 +01:00