278 lines
8.6 KiB
C
278 lines
8.6 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include "inteltool.h"
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volatile uint8_t *mchbar;
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static void write_mchbar32 (uint32_t addr, uint32_t val)
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{
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* (volatile uint32_t *) (mchbar + addr) = val;
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}
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static uint32_t read_mchbar32 (uint32_t addr)
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{
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return * (volatile uint32_t *) (mchbar + addr);
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}
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static uint8_t read_mchbar8 (uint32_t addr)
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{
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return * (volatile uint8_t *) (mchbar + addr);
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}
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static u16 read_500 (int channel, u16 addr, int split)
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{
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uint32_t val;
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write_mchbar32 (0x500 + (channel << 10), 0);
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while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
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write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr));
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while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000);
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val = read_mchbar32 (0x508 + (channel << 10));
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return val & ((1 << split) - 1);
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}
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static inline u16 get_lane_offset (int slot, int rank, int lane)
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{
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return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8);
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}
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static inline u16 get_timing_register_addr (int lane, int tm, int slot, int rank)
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{
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const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c };
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return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4];
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}
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static void write_1d0 (u32 val, u16 addr, int bits, int flag)
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{
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write_mchbar32 (0x1d0, 0);
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while (read_mchbar32 (0x1d0) & 0x800000);
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write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits));
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write_mchbar32 (0x1d0, 0x40000000 | addr);
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while (read_mchbar32 (0x1d0) & 0x800000);
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}
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static u16 read_1d0 (u16 addr, int split)
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{
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u32 val;
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write_mchbar32 (0x1d0, 0);
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while (read_mchbar32 (0x1d0) & 0x800000);
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write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr));
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while (read_mchbar32 (0x1d0) & 0x800000);
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val = read_mchbar32 (0x1d8);
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write_1d0 (0, 0x33d, 0, 0);
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write_1d0 (0, 0x33d, 0, 0);
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return val & ((1 << split) - 1);
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}
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static void dump_timings (void)
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{
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int channel, slot, rank, lane, i;
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printf ("Timings:\n");
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for (channel = 0; channel < 2; channel++)
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for (slot = 0; slot < 2; slot++)
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for (rank = 0; rank < 2; rank++) {
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printf ("channel %d, slot %d, rank %d\n", channel, slot, rank);
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for (lane = 0; lane < 9; lane++) {
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printf ("lane %d: ", lane);
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for (i = 0; i < 4; i++) {
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printf ("%x ", read_500 (channel,
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get_timing_register_addr (lane, i, slot, rank), 9));
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}
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printf ("\n");
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}
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}
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printf ("[178] = %x\n", read_1d0 (0x178, 7));
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printf ("[10b] = %x\n", read_1d0 (0x10b, 6));
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}
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/*
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* (G)MCH MMIO Config Space
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*/
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int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file)
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{
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int i, size = (16 * 1024);
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uint64_t mchbar_phys;
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struct pci_dev *nb_device6; /* "overflow device" on i865 */
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uint16_t pcicmd6;
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printf("\n============= MCHBAR ============\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82865:
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/*
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* On i865, the memory access enable/disable bit (MCHBAREN on
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* i945/i965) is not in the MCHBAR (i945/i965) register but in
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* the PCICMD6 register. BAR6 and PCICMD6 reside on device 6.
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*
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* The actual base address is in BAR6 on i865 where on
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* i945/i965 the base address is in MCHBAR.
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*/
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nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */
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mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */
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pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */
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/* Try to enable Memory Access Enable (MAE). */
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if (!(pcicmd6 & (1 << 1))) {
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printf("Access to BAR6 is currently disabled, "
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"attempting to enable.\n");
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pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1));
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if (pci_read_long(nb_device6, 0x04) & (1 << 1))
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printf("Enabled successfully.\n");
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else
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printf("Enable FAILED!\n");
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}
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mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */
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break;
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case PCI_DEVICE_ID_INTEL_82915:
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case PCI_DEVICE_ID_INTEL_82945GM:
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case PCI_DEVICE_ID_INTEL_82945GSE:
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case PCI_DEVICE_ID_INTEL_82945P:
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case PCI_DEVICE_ID_INTEL_82975X:
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_82965PM:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82946:
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case PCI_DEVICE_ID_INTEL_82Q965:
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case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
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case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
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mchbar_phys = pci_read_long(nb, 0x48);
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/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
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* If it isn't, try to set it. This may fail, because there is
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* some bit that locks that bit, and isn't in the public
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* datasheets.
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*/
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if(!(mchbar_phys & 1))
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{
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printf("Access to the MCHBAR is currently disabled, "
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"attempting to enable.\n");
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mchbar_phys |= 0x1;
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pci_write_long(nb, 0x48, mchbar_phys);
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if(pci_read_long(nb, 0x48) & 1)
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printf("Enabled successfully.\n");
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else
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printf("Enable FAILED!\n");
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}
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mchbar_phys &= 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82443LX:
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case PCI_DEVICE_ID_INTEL_82443BX:
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810E_DC:
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case PCI_DEVICE_ID_INTEL_82810_DC:
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case PCI_DEVICE_ID_INTEL_82830M:
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printf("This northbridge does not have MCHBAR.\n");
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return 1;
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case PCI_DEVICE_ID_INTEL_82XX4X:
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case PCI_DEVICE_ID_INTEL_82Q45:
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case PCI_DEVICE_ID_INTEL_82G45:
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case PCI_DEVICE_ID_INTEL_82G41:
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case PCI_DEVICE_ID_INTEL_82B43:
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case PCI_DEVICE_ID_INTEL_82B43_2:
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case PCI_DEVICE_ID_INTEL_82X38:
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case PCI_DEVICE_ID_INTEL_32X0:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
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mchbar_phys = pci_read_long(nb, 0x48);
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
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break;
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
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case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
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mchbar_phys = pci_read_long(nb, 0x48);
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
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size = 32768;
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break;
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default:
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printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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mchbar = map_physical(mchbar_phys, size);
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if (mchbar == NULL) {
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if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
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perror("Error mapping BAR6");
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else
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perror("Error mapping MCHBAR");
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exit(1);
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}
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if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
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printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
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else
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printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(mchbar + i))
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printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i));
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}
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switch (nb->device_id)
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{
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case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
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printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
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dump_timings ();
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if (dump_spd_file != NULL)
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printf("\nCreating a memory timings file is not supported on this chipset.\n");
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break;
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
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ivybridge_dump_timings(dump_spd_file);
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break;
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default:
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if (dump_spd_file != NULL)
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printf("\nCreating a memory timings file is not supported on this chipset.\n");
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}
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unmap_physical((void *)mchbar, size);
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return 0;
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}
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