177 lines
3.9 KiB
Plaintext
177 lines
3.9 KiB
Plaintext
# Sample config file for Motorola Sandpoint X3 Demo Board with
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# the Arima HDAMA
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# This will make a target directory of ./hdama
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loadoptions
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target ./hdama
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uses CONFIG_COMPRESS
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uses CONFIG_IOAPIC
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses ENABLE_FIXED_AND_VARIABLE_MTRRS
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uses FALLBACK_SIZE
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uses FINAL_MAINBOARD_FIXUP
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uses HAVE_FALLBACK_BOOT
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses HEAP_SIZE
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uses IRQ_SLOT_COUNT
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAX_CPUS
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uses MEMORY_HOLE
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uses PAYLOAD_SIZE
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uses _RAMBASE
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uses _ROMBASE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_OFFSET
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uses ROM_SECTION_SIZE
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uses ROM_SIZE
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uses SIO_BASE
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uses SIO_SYSTEM_CLK_INPUT
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uses STACK_SIZE
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uses USE_ELF_BOOT
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uses USE_FALLBACK_IMAGE
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uses USE_OPTION_TABLE
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option HAVE_MP_TABLE=0
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### Customize our winbond superio chip for this motherboard
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###
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option SIO_BASE=0x2e
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option SIO_SYSTEM_CLK_INPUT=0
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#
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###
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### Build code for the fallback boot
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###
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option HAVE_FALLBACK_BOOT=1
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#
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###
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### Build code to export a programmable irq routing table
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###
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=7
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#
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###
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### Build code for SMP support
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### Only worry about 2 micro processors
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###
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##option CONFIG_SMP=1
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option MAX_CPUS=1
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#
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###
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### Build code to setup a generic IOAPIC
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###
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option CONFIG_IOAPIC=1
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#
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###
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### MEMORY_HOLE instructs earlymtrr.inc to
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### enable caching from 0-640KB and to disable
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### caching from 640KB-1MB using fixed MTRRs
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###
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### Enabling this option breaks SMP because secondary
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### CPU identification depends on only variable MTRRs
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### being enabled.
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###
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option MEMORY_HOLE=0
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#
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###
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### Enable both fixed and variable MTRRS
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### When we setup MTRRs in mtrr.c
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###
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### We must setup the fixed mtrrs or we confuse SMP secondary
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### processor identification
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###
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option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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#
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###
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### Clean up the motherboard id strings
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###
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#option MAINBOARD_PART_NUMBER="Solo7"
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#option MAINBOARD_VENDOR="AMD"
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#
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###
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### Call the final_mainboard_fixup function
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###
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option FINAL_MAINBOARD_FIXUP=1
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option USE_FALLBACK_IMAGE=0
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###
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### Only use the option table in a normal image
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###
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option USE_OPTION_TABLE=!USE_FALLBACK_IMAGE
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#
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###
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### Compute the location and size of where this firmware image
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### (linuxBIOS plus bootloader) will live in the boot rom chip.
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###
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#if USE_FALLBACK_IMAGE
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# option ROM_SECTION_SIZE = FALLBACK_SIZE
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# option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
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#end
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#if USE_NORMAL_IMAGE
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# option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
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# option ROM_SECTION_OFFSET= 0
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#end
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###
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### Compute where this copy of linuxBIOS will start in the boot rom
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###
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#
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###
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### Compute a range of ROM that can cached to speed up linuxBIOS,
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### execution speed.
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###
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##expr XIP_ROM_SIZE = 65536
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##expr XIP_ROM_BASE = _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE
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##option XIP_ROM_SIZE=65536
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##option XIP_ROM_BASE=0xffff0000
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#
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## XIP_ROM_SIZE && XIP_ROM_BASE values that work.
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##option XIP_ROM_SIZE=0x8000
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##option XIP_ROM_BASE=0xffff8000
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## We don't use compressed image
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option CONFIG_COMPRESS=0
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option USE_ELF_BOOT=1
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option ROM_SIZE=524288
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE=49152
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00100000
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##
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## Use a 64K stack
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##
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option STACK_SIZE=0x10000
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##
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## Use a 64K heap
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##
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option HEAP_SIZE=0x10000
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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option ROM_SECTION_SIZE=ROM_SIZE
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option ROM_SECTION_OFFSET=0
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#
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###
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### Compute the start location and size size of
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### The linuxBIOS bootloader.
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###
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option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
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option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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option CONFIG_ROM_STREAM = 1
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option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
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#
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# Arima hdama
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mainboard arima/hdama
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makedefine CFLAGS += -g
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end
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