efa606b77b
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/rtc.h>
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#include <pc80/mc146818rtc.h>
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#include <soc/gpio.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include <vboot/vbnv.h>
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#include "chip.h"
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static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = {
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{ 0xfed40000, 0x8000 },
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{ 0xfedc0000, 0x4000 },
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{ 0xfed20800, 16 },
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{ 0xfed20880, 8 },
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{ 0xfed208e0, 16 },
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{ 0xfed208f0, 8 },
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{ 0xfed30800, 16 },
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{ 0xfed30880, 8 },
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{ 0xfed308e0, 16 },
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{ 0xfed308f0, 8 },
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{ 0, 0 }
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};
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const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
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{
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return apl_lpc_fixed_mmio_ranges;
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}
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static const struct pad_config lpc_gpios[] = {
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#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
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PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_CLKOUT0 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_CLKOUT1 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_AD0 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_AD1 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_AD2 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_AD3 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_154, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_CLKRUNB */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_FRAMEB*/
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#else
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PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
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#endif
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};
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void lpc_configure_pads(void)
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{
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gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
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}
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static void rtc_init(void)
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{
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int rtc_fail;
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const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (!ps) {
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printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n");
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return;
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}
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rtc_fail = !!(ps->gen_pmcon1 & RPS);
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/* Ensure the date is set including century byte. */
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cmos_check_update_date();
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if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS))
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init_vbnv_cmos(rtc_fail);
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else
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cmos_init(rtc_fail);
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}
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void lpc_init(struct device *dev)
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{
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const struct soc_intel_apollolake_config *cfg;
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cfg = dev->chip_info;
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if (!cfg) {
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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return;
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}
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/* Set LPC Serial IRQ mode */
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lpc_set_serirq_mode(cfg->serirq_mode);
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/* Initialize RTC */
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rtc_init();
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}
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