Johnny Lin d4698d94af soc/xeon_sp/cpx: Define MSR PPIN related registers ... These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Tested on OCP DeltaLake with change https://review.coreboot.org/c/coreboot/+/40308/ Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>		2020-06-28 21:44:27 +00:00
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amd	soc/amd/picasso/soc_util: rework reduced I/O chip detection	2020-06-28 14:16:36 +00:00
cavium	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
intel	soc/xeon_sp/cpx: Define MSR PPIN related registers	2020-06-28 21:44:27 +00:00
mediatek	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
nvidia	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
qualcomm	soc/qualcomm/sc7180/qupv3_config.c: Add missing includes	2020-06-22 11:49:34 +00:00
rockchip	soc/rockchip: Use (Q) instead of @	2020-06-26 21:13:33 +00:00
samsung	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
sifive	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	2020-06-13 06:49:23 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00