0f2dd1eff9
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
91 lines
3 KiB
C
91 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <device/i2c_simple.h>
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#include <soc/addressmap.h>
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#include <soc/clk_rst.h>
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#include <soc/clock.h>
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#include <soc/funitcfg.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/padconfig.h>
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#include <soc/spi.h> /* FIXME: move back to soc code? */
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#include "pmic.h"
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static const struct pad_config pmic_pads[] = {
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PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
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PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
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};
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static const struct pad_config spiflash_pads[] = {
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/* QSPI fLash: mosi, miso, clk, cs0, hold, wp */
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PAD_CFG_SFIO(QSPI_IO0, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
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PAD_CFG_SFIO(QSPI_IO1, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
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PAD_CFG_SFIO(QSPI_SCK, PINMUX_INPUT_ENABLE, QSPI),
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PAD_CFG_SFIO(QSPI_CS_N, PINMUX_INPUT_ENABLE, QSPI),
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PAD_CFG_SFIO(QSPI_IO2, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
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PAD_CFG_SFIO(QSPI_IO3, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, QSPI),
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};
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/********************* TPM ************************************/
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static const struct pad_config tpm_pads[] = {
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PAD_CFG_SFIO(GEN3_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
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PAD_CFG_SFIO(GEN3_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
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};
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static const struct funit_cfg funits[] = {
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/* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */
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FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)),
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/* SPI flash at 24MHz on QSPI controller. */
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FUNIT_CFG(QSPI, PLLP, 24000, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
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/* Foster has no TPM yet. This is for futurn TPM on I2C3 @ 400kHz. */
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FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
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};
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static const struct pad_config uart_console_pads[] = {
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/* UARTA: tx, rx, rts, cts */
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PAD_CFG_SFIO(UART1_TX, PINMUX_PULL_NONE, UARTA),
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PAD_CFG_SFIO(UART1_RX, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UARTA),
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PAD_CFG_SFIO(UART1_RTS, PINMUX_PULL_UP, UARTA),
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PAD_CFG_SFIO(UART1_CTS, PINMUX_PULL_UP, UARTA),
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};
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void bootblock_mainboard_early_init(void)
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{
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soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
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}
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static void set_clock_sources(void)
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{
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/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
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write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
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}
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void bootblock_mainboard_init(void)
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{
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set_clock_sources();
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soc_configure_funits(funits, ARRAY_SIZE(funits));
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i2c_init(I2CPWR_BUS);
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pmic_init(I2CPWR_BUS);
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/* Foster has no TPM yet. This is for future TPM. */
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i2c_init(I2C3_BUS);
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}
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