Maulik V Vaghela 85d9f47014 Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods" ... This reverts commit 1399442289. Reason for revert: Some Cr50 chips with old firmware version (x.y.22) don't support long pulse interrupt command, requiring dynamic GPIO PM to be disabled to intercept short pulse interrupt. Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods to support power gating of GPIO communities from the kernel when dynamic GPIO PM is disabled. BUG=b:204832081 BRANCH=None Test= S0ix works with dynamic PM disabled. Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/58811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>		2021-11-17 15:54:10 +00:00
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camera_clock_ctl.asl
dptf.asl
gpio.asl	Revert "soc/intel/adl: Drop SGPM, RGPM and EGPM methods"	2021-11-17 15:54:10 +00:00
pch_hda.asl
pcie.asl
serialio.asl	soc/intel/alderlake: Add support for I2C6 and I2C7	2021-07-20 13:35:10 +00:00
southbridge.asl	soc/intel/alderlake: Switch to runtime generation of Intel Power Engine	2021-09-10 21:53:32 +00:00
tcss.asl	src/soc to src/superio: Fix spelling errors	2021-10-05 18:07:08 +00:00
tcss_dma.asl	soc/intel/alderlake: Fix processor hang while plug unplug of TBT device	2021-09-01 16:46:27 +00:00
tcss_pcierp.asl	soc/intel/alderlake: Add ACPI addition for USB4/TBT latency optimization	2021-10-29 16:53:57 +00:00
tcss_xhci.asl
xhci.asl