20a609f0f7
To avoid duplicating this function in ramstage, factor it out. Change-Id: I64c59a01ca153770481c28ae404a5dfe8c5382d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Nico Huber <nico.h@gmx.de>
31 lines
617 B
C
31 lines
617 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#define __SIMPLE_DEVICE__
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#include <device/pci_ops.h>
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#include <types.h>
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#include "me.h"
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#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
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#define ETR3 0xac
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#define ETR3_CWORWRE (1 << 18)
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#define ETR3_CF9GR (1 << 20)
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#define ETR3_CF9LOCK (1 << 31)
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void set_global_reset(const bool enable)
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{
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u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
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/* Clear CF9 Without Resume Well Reset Enable */
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etr3 &= ~ETR3_CWORWRE;
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/* CF9GR indicates a Global Reset */
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if (enable)
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etr3 |= ETR3_CF9GR;
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else
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etr3 &= ~ETR3_CF9GR;
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pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
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}
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