coreboot-kgpe-d16/src/southbridge/intel/common/pmbase.c
Patrick Georgi 6b5bc77c9b treewide: Remove "this file is part of" lines
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 17:11:40 +00:00

93 lines
1.7 KiB
C

/* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <acpi/acpi.h>
#include <arch/io.h>
#include <bootmode.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <assert.h>
#include "pmbase.h"
#include "pmutil.h"
/* LPC PM Base Address Register */
#define PMBASE 0x40
#define PMSIZE 0x80
/* PCI Configuration Space (D31:F0): LPC */
#if defined(__SIMPLE_DEVICE__)
#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
#else
#define PCH_LPC_DEV pcidev_on_root(0x1f, 0)
#endif
u16 lpc_get_pmbase(void)
{
#ifdef __SIMPLE_DEVICE__
/* Don't assume PMBASE is still the same */
return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
#else
static u16 pmbase;
if (pmbase)
return pmbase;
pmbase = pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
return pmbase;
#endif
}
void write_pmbase32(const u8 addr, const u32 val)
{
ASSERT(addr <= (PMSIZE - sizeof(u32)));
outl(val, lpc_get_pmbase() + addr);
}
void write_pmbase16(const u8 addr, const u16 val)
{
ASSERT(addr <= (PMSIZE - sizeof(u16)));
outw(val, lpc_get_pmbase() + addr);
}
void write_pmbase8(const u8 addr, const u8 val)
{
ASSERT(addr <= (PMSIZE - sizeof(u8)));
outb(val, lpc_get_pmbase() + addr);
}
u32 read_pmbase32(const u8 addr)
{
ASSERT(addr <= (PMSIZE - sizeof(u32)));
return inl(lpc_get_pmbase() + addr);
}
u16 read_pmbase16(const u8 addr)
{
ASSERT(addr <= (PMSIZE - sizeof(u16)));
return inw(lpc_get_pmbase() + addr);
}
u8 read_pmbase8(const u8 addr)
{
ASSERT(addr <= (PMSIZE - sizeof(u8)));
return inb(lpc_get_pmbase() + addr);
}
int platform_is_resuming(void)
{
u16 reg16 = read_pmbase16(PM1_STS);
if (!(reg16 & WAK_STS))
return 0;
return acpi_sleep_from_pm1(reg16) == ACPI_S3;
}