6e732d34a0
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases where a pointer cast would be necessary. Instances in Sandy Bridge MRC code were left as-is intentionally, so as not to collide with another cleanup patch train. Tested with BUILD_TIMELESS=1, these boards remain identical: - Asus P8Z77-V LX2 - Packard Bell MS2290 Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/smbus_host.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/common/pmbase.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801jx.h"
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#include "chip.h"
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void i82801jx_lpc_setup(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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const struct device *dev = pcidev_on_root(0x1f, 0);
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const struct southbridge_intel_i82801jx_config *config;
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/* Configure serial IRQs.*/
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pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0);
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/*
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* Enable some common LPC IO ranges:
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* - 0x2e/0x2f, 0x4e/0x4f often SuperIO
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* - 0x60/0x64, 0x62/0x66 often KBC/EC
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* - 0x3f0-0x3f5/0x3f7 FDD
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* - 0x378-0x37f and 0x778-0x77f LPT
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* - 0x2f8-0x2ff COMB
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* - 0x3f8-0x3ff COMA
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* - 0x208-0x20f GAMEH
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* - 0x200-0x207 GAMEL
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*/
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pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010);
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pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
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| MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
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| GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
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| COMB_LPC_EN | COMA_LPC_EN);
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/* Set up generic decode ranges */
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if (!dev || !dev->chip_info)
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return;
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config = dev->chip_info;
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pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec);
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pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec);
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pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
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pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
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}
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void i82801jx_setup_bars(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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/* Set up RCBA. */
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pci_write_config32(d31f0, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1);
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/* Set up PMBASE. */
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pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
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/* Enable PMBASE. */
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pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80);
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/* Set up GPIOBASE. */
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pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE);
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/* Enable GPIO. */
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pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10);
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}
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#define TCO_BASE 0x60
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void i82801jx_early_init(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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if (ENV_ROMSTAGE)
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enable_smbus();
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printk(BIOS_DEBUG, "Setting up static southbridge registers...");
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i82801jx_setup_bars();
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printk(BIOS_DEBUG, " done.\n");
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setup_pch_gpios(&mainboard_gpio_map);
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printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
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RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
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write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */
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write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */
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write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */
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printk(BIOS_DEBUG, " done.\n");
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/* Enable IOAPIC */
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RCBA8(OIC) = 0x3;
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RCBA8(OIC);
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/* Initialize power management initialization
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register early as it affects reboot behavior. */
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/* Bit 20 activates global reset of host and ME on cf9 writes of 0x6
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and 0xe (required if ME is disabled but present), bit 31 locks it.
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The other bits are 'must write'. */
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u8 reg8 = pci_read_config8(d31f0, 0xac);
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/* FIXME: It's a 8-bit variable!!! */
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reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);
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pci_write_config8(d31f0, 0xac, reg8);
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/* TODO: If RTC power failed, reset RTC state machine
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(set, then reset RTC 0x0b bit7) */
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/* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
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before they get cleared. */
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}
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