9018dee685
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
96 lines
2.6 KiB
C
96 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <cpu/cpu.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <fsp/util.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/systemagent.h>
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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/* Add VTd resources if VTd is enabled. These resources were
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set up by the FSP-S call. */
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
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return;
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if (MCHBAR32(GFXVTBAR) & VTBAR_ENABLED) {
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mmio_resource_kb(dev, *index,
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(MCHBAR64(GFXVTBAR) & VTBAR_MASK) / KiB,
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VTBAR_SIZE / KiB);
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(*index)++;
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}
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if (MCHBAR32(DEFVTBAR) & VTBAR_ENABLED) {
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mmio_resource_kb(dev, *index,
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(MCHBAR64(DEFVTBAR) & VTBAR_MASK) / KiB,
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VTBAR_SIZE / KiB);
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(*index)++;
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}
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}
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int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
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uint64_t *prmrr_mask)
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{
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const void *hob;
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size_t hob_size, prmrr_size;
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uint64_t phys_address_mask;
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const uint8_t prmrr_phys_base_guid[16] = {
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0x38, 0x3a, 0x81, 0x9f, 0xb0, 0x6f, 0xa7, 0x4f,
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0xaf, 0x79, 0x8a, 0x4e, 0x74, 0xdd, 0x48, 0x33
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};
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const uint8_t prmrr_size_guid[16] = {
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0x44, 0xed, 0x0b, 0x99, 0x4e, 0x9b, 0x26, 0x42,
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0xa5, 0x97, 0x28, 0x36, 0x76, 0x6b, 0x5c, 0x41
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};
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hob = fsp_find_extension_hob_by_guid(prmrr_phys_base_guid,
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&hob_size);
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if (!hob) {
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printk(BIOS_ERR, "Failed to locate PRMRR base hob\n");
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return -1;
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}
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if (hob_size != sizeof(uint64_t)) {
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printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
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return -1;
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}
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*prmrr_base = *(uint64_t *)hob;
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hob = fsp_find_extension_hob_by_guid(prmrr_size_guid,
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&hob_size);
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if (!hob) {
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printk(BIOS_ERR, "Failed to locate PRMRR size hob\n");
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return -1;
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}
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if (hob_size != sizeof(uint64_t)) {
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printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
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return -1;
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}
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prmrr_size = *(uint64_t *)hob;
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phys_address_mask = (1ULL << cpu_phys_address_size()) - 1;
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*prmrr_mask = phys_address_mask & ~(uint64_t)(prmrr_size - 1);
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return 0;
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}
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uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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{
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/* Max 4GiB per rank, 2 ranks per channel. Intel Document: 332092-002 */
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return 8192;
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}
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