coreboot-kgpe-d16/src/southbridge
Duncan Laurie 54cba3b4ad SMM: Skip locking SPI registers in finalize step
This is a temporary workaround so the SPI bus can be accessed
at runtime in SMM code until the SPI opcode menu is used
properly.

Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1318
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25 22:59:43 +02:00
..
amd cs5536: add smbus support in ramstage 2012-07-24 12:18:28 +02:00
broadcom Clean up #ifs 2012-05-08 00:34:34 +02:00
intel SMM: Skip locking SPI registers in finalize step 2012-07-25 22:59:43 +02:00
nvidia Don't use 64-bit constant 0x100000000 in linker scripts 2012-06-21 08:05:31 +02:00
rdc Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00
ricoh add functions to set Subsystem Vendor/Device to rl5c746 2011-02-28 18:09:58 +00:00
sis Don't use 64-bit constant 0x100000000 in linker scripts 2012-06-21 08:05:31 +02:00
ti remove trailing whitespace 2011-11-01 19:07:45 +01:00
via Define global uma_memory variables 2012-07-16 18:41:46 +02:00
Kconfig Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00
Makefile.inc Add support for RDC R8610 Southbridge 2012-03-27 18:39:05 +02:00