551a75923e
Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/common/pmbase.h>
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#include <southbridge/intel/common/tco.h>
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#include <watchdog.h>
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/*
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* Disable ICH-NM10-PCH watchdog timer
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*/
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void watchdog_off(void)
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{
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unsigned int value;
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struct device *dev;
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/* Get LPC device. */
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dev = pcidev_on_root(0x1f, 0);
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value = pci_read_config16(dev, PCI_COMMAND);
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if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) {
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/* Enable I/O space. */
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value |= PCI_COMMAND_IO;
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} else {
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/* Disable interrupt. */
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value |= PCI_COMMAND_INT_DISABLE;
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}
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pci_write_config16(dev, PCI_COMMAND, value);
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/* Disable the watchdog timer. */
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value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
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value |= TCO_TMR_HLT;
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write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
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/* Clear TCO timeout status. */
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write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
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write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
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printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");
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}
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