43b7f41678
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
97 lines
2.8 KiB
C
97 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <commonlib/helpers.h>
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#include <device/mmio.h>
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#include <device/pci_rom.h>
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#include <device/resource.h>
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#include <drivers/intel/gma/i915.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <intelblocks/graphics.h>
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#include <soc/ramstage.h>
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#include <soc/systemagent.h>
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#include <types.h>
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void graphics_soc_panel_init(struct device *dev)
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{
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struct soc_intel_skylake_config *conf = config_of(dev);
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const struct i915_gpu_panel_config *panel_cfg;
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struct resource *mmio_res;
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uint8_t *base;
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u32 reg32;
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if (!conf)
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return;
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panel_cfg = &conf->panel_cfg;
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mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
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if (!mmio_res || !mmio_res->base)
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return;
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base = (void *)(uintptr_t)mmio_res->base;
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reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
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reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
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write32(base + PCH_PP_ON_DELAYS, reg32);
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reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
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reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
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write32(base + PCH_PP_OFF_DELAYS, reg32);
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reg32 = read32(base + PCH_PP_DIVISOR);
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reg32 &= ~0x1f;
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reg32 |= (DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f;
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write32(base + PCH_PP_DIVISOR, reg32);
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/* So far all devices seem to use the PCH PWM function.
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The CPU PWM registers are all zero after reset. */
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if (panel_cfg->backlight_pwm_hz) {
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/* Reference clock is 24MHz. We can choose either a 16
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or a 128 step increment. Use 16 if we would have less
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than 100 steps otherwise. */
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const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
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unsigned int pwm_increment, pwm_period;
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u32 south_chicken1;
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south_chicken1 = read32(base + SOUTH_CHICKEN1);
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if (panel_cfg->backlight_pwm_hz > hz_limit) {
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pwm_increment = 16;
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south_chicken1 &= ~1;
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} else {
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pwm_increment = 128;
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south_chicken1 |= 1;
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}
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write32(base + SOUTH_CHICKEN1, south_chicken1);
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pwm_period = 24 * 1000 * 1000 / pwm_increment / panel_cfg->backlight_pwm_hz;
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/* Start with a 50% duty cycle. */
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write32(base + BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
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write32(base + BLC_PWM_PCH_CTL1,
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!!panel_cfg->backlight_polarity << 29 | BLM_PCH_PWM_ENABLE);
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}
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}
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const struct i915_gpu_controller_info *
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intel_igd_get_controller_info(const struct device *device)
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{
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struct soc_intel_skylake_config *chip = device->chip_info;
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return &chip->gfx;
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}
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/*
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* Some VGA option roms are used for several chipsets but they only have one PCI ID in their
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* header. If we encounter such an option rom, we need to do the mapping ourselves.
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*/
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u32 map_oprom_vendev(u32 vendev)
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{
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u32 new_vendev = vendev;
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switch (vendev) {
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case 0x80865916: /* PCI_DID_INTEL_KBL_GT2_SULTM */
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case 0x80865917: /* PCI_DID_INTEL_KBL_GT2_SULTMR */
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new_vendev = SA_IGD_OPROM_VENDEV;
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break;
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}
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return new_vendev;
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}
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