coreboot-kgpe-d16/src
Vadim Bendebury 5554d1cf8a rk3399: add ability to configure SPI5
This defines mux settings for the GPIO bank responsible for SPI
interface #5.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied it is possible to
     communicate with the EC on gru: pressing Ctrl-U during boot
     allows to start Chrome OS from the SD card.

Change-Id: Ibc2293b5662892f7b275434f9a672ef68edf4f9e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4f92452
Original-Change-Id: Idf55c069b05492f8cdc204a8c273e39a19a3aef3
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/346630
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/15030
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08 23:20:18 +02:00
..
acpi
arch SMBIOS: Implement SKU field 2016-06-02 06:24:24 +02:00
commonlib commonlib/lz4: Avoid unaligned memory access on RISC-V 2016-05-31 21:07:03 +02:00
console console/post: be explicit about conditional cmos_post_log() compiling 2016-05-25 18:04:11 +02:00
cpu AGESA vendorcode: Build a common amdlib 2016-05-18 10:44:43 +02:00
device device: Add an ACPI device name and path concept to devices 2016-05-21 05:59:52 +02:00
drivers drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header 2016-06-08 22:35:18 +02:00
ec chromeec: Move EC image hash to separate file in CBFS 2016-06-03 17:24:26 +02:00
include SMBIOS: Implement SKU field 2016-06-02 06:24:24 +02:00
lib cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP 2016-06-02 17:21:39 +02:00
mainboard gru: kevin: define GPIOs used on both platforms 2016-06-08 23:19:32 +02:00
northbridge nb/intel/x4x: Fix unpopulated value 2016-06-04 23:46:05 +02:00
soc rk3399: add ability to configure SPI5 2016-06-08 23:20:18 +02:00
southbridge drivers/lenovo: Add hybrid graphics driver 2016-06-01 23:22:01 +02:00
superio sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-29 19:34:54 +02:00
vendorcode AGESA boards: Split dispatcher to romstage and ramstage 2016-06-04 23:44:33 +02:00
Kconfig Add Board Checklist Support 2016-06-03 17:29:13 +02:00