CK Hu 5559a449d4 soc/mediatek/mt8192: Initialize build rules ... The first Makefile to support building minimal stage files for MT8192 SOC. Signed-off-by: CK Hu <ck.hu@mediatek.com> Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43962 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-08-13 05:33:57 +00:00
..
acpi	src/acpi: Add missing <{stdbool,stdint}.h>	2020-07-29 09:37:10 +00:00
arch	arch/x86/pirq_routing.c: Drop unneeded `continue`	2020-08-06 11:22:11 +00:00
commonlib	src: Remove unused 'include <stdint.h>	2020-07-14 16:11:10 +00:00
console	…
cpu	cpu/intel: Remove Core 2 Duo E8200 CPUID from model_6fx	2020-08-11 21:43:47 +00:00
device	src: Use space after 'if', 'for'	2020-08-05 11:37:00 +00:00
drivers	drivers/intel/fsp2_0: Fill EFI_CPU_PHYSICAL_LOCATION structure information	2020-08-13 02:39:51 +00:00
ec	ec/lenovo/h8: Align macro values in one column	2020-07-26 21:40:00 +00:00
include	soc/intel/common: Include Alder Lake SATA controller device IDs	2020-08-10 06:30:39 +00:00
lib	gpio: Pull down HiZ pins after reading tristate GPIO strapping	2020-08-06 23:54:41 +00:00
mainboard	mb/google/zork: Update PICASSO_FW_*_POSITION to match new layout	2020-08-13 04:02:28 +00:00
northbridge	nb/intel/sandybridge: Add comments to `struct iosav_ssq`	2020-08-12 11:01:44 +00:00
security	security/intel/txt: Fix variable MTRR handling	2020-08-07 11:56:29 +00:00
soc	soc/mediatek/mt8192: Initialize build rules	2020-08-13 05:33:57 +00:00
southbridge	sb/intel/bd82x6x: Make `pch_silicon_supported` static	2020-08-12 11:02:34 +00:00
superio	superio/ite: allow 24 MHz clock for external sensor interface	2020-08-10 12:44:17 +00:00
vendorcode	vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3313	2020-08-13 02:16:56 +00:00
Kconfig	arch/x86: Remove RELOCATABLE_RAMSTAGE	2020-07-06 06:17:47 +00:00