8d5cedf046
The three mainboards using this southbridge are desktop boards, which are not dockable. The Dell Precision M6400 laptop is dockable, but even though it has an Eaglelake MCH, it uses an i82801ix southbridge instead. So, one could still port that laptop to coreboot after this change! :P Also, drop the now-unnecessary `chip` and `dev` variables. Change-Id: Ic9ab497c91d66032929190cde22d59a208887f50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
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#define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
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#include <stdint.h>
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enum {
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THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3,
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THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7
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};
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struct southbridge_intel_i82801jx_config {
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/**
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* GPI Routing configuration
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*
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* Only the lower two bits have a meaning:
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* 00: No effect
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* 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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* 10: SCI (if corresponding GPIO_EN bit is also set)
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* 11: reserved
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*/
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uint8_t gpi0_routing;
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uint8_t gpi1_routing;
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uint8_t gpi2_routing;
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uint8_t gpi3_routing;
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uint8_t gpi4_routing;
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uint8_t gpi5_routing;
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uint8_t gpi6_routing;
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uint8_t gpi7_routing;
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uint8_t gpi8_routing;
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uint8_t gpi9_routing;
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uint8_t gpi10_routing;
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uint8_t gpi11_routing;
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uint8_t gpi12_routing;
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uint8_t gpi13_routing;
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uint8_t gpi14_routing;
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uint8_t gpi15_routing;
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uint32_t gpe0_en;
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uint16_t alt_gp_smi_en;
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/* IDE configuration */
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uint8_t sata_port_map : 6;
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int sata_clock_request : 1;
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int sata_traffic_monitor : 1;
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int c4onc3_enable:1;
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int c5_enable : 1;
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int c6_enable : 1;
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int throttle_duty : 3;
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/* Bit mask to tell whether a PCIe slot is implemented as slot. */
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int pcie_slot_implemented : 6;
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/* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
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struct {
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uint8_t value : 8;
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uint8_t scale : 2;
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} pcie_power_limits[6];
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uint8_t pcie_hotplug_map[8];
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/* Additional LPC IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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};
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#endif /* SOUTHBRIDGE_INTEL_I82801JX_CHIP_H */
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