fca0cba6a1
The smm_setup_structures() calls placed GNVS address into register %ebx. Old code on i82801dx used these low memory addresses. Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42426 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <types.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/pmutil.h>
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#include "i82801jx.h"
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#include "nvs.h"
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/* While we read PMBASE dynamically in case it changed, let's
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* initialize it with a sane value
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*/
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u16 pmbase = DEFAULT_PMBASE;
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u8 smm_initialized = 0;
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/* This implementation was removed since it was invalid. There will be one shared
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approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */
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void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
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int southbridge_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x32:
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printk(BIOS_DEBUG, "OS Init\n");
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/* gnvs->smif:
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* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*/
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gnvs->smif = 0;
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return 1; /* IO trap handled */
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}
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/* Not handled */
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return 0;
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}
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void southbridge_smi_monitor(void)
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{
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#define IOTRAP(x) (trap_sts & (1 << x))
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u32 trap_sts, trap_cycle;
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u32 data, mask = 0;
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int i;
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trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
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RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
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trap_cycle = RCBA32(0x1e10);
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for (i=16; i<20; i++) {
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if (trap_cycle & (1 << i))
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mask |= (0xff << ((i - 16) << 3));
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}
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/* IOTRAP(3) SMI function call */
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if (IOTRAP(3)) {
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if (gnvs && gnvs->smif)
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io_trap_handler(gnvs->smif); // call function smif
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return;
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}
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/* IOTRAP(2) currently unused
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* IOTRAP(1) currently unused */
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/* IOTRAP(0) SMIC */
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if (IOTRAP(0)) {
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if (!(trap_cycle & (1 << 24))) { // It's a write
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printk(BIOS_DEBUG, "SMI1 command\n");
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data = RCBA32(0x1e18);
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data &= mask;
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// if (smi1)
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// southbridge_smi_command(data);
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// return;
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}
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// Fall through to debug
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}
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printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
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for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
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printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
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printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
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printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
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if (!(trap_cycle & (1 << 24))) {
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/* Write Cycle */
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data = RCBA32(0x1e18);
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printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
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}
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#undef IOTRAP
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}
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void southbridge_finalize_all(void)
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{
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}
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