9234d9231b
Some boards with the chrome EC will need to support more than 4 temperature sensors, so modify the number of TSRs supported when generating the ACPI code. Note that the EC memory map already has support for up to 16 TSRs, so no change is required on the EC side. BUG=b:207585491 TEST=with previous patch and some test data in brya0 overridetree.cb, dump the SSDT and verify that all of the existing Methods for TSR0-TSR3 are also added for TSR4, as well as all Notify, etc. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59633 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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