1321 lines
36 KiB
Plaintext
1321 lines
36 KiB
Plaintext
## SPDX-License-Identifier: GPL-2.0-only
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mainmenu "coreboot configuration"
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menu "General setup"
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config COREBOOT_BUILD
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bool
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default y
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config LOCALVERSION
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string "Local version string"
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help
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Append an extra string to the end of the coreboot version.
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This can be useful if, for instance, you want to append the
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respective board's hostname or some other identifying string to
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the coreboot version number, so that you can easily distinguish
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boot logs of different boards from each other.
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config CONFIGURABLE_CBFS_PREFIX
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bool
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help
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Select this to prompt to use to configure the prefix for cbfs files.
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choice
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prompt "CBFS prefix to use"
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depends on CONFIGURABLE_CBFS_PREFIX
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default CBFS_PREFIX_FALLBACK
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config CBFS_PREFIX_FALLBACK
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bool "fallback"
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config CBFS_PREFIX_NORMAL
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bool "normal"
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config CBFS_PREFIX_DIY
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bool "Define your own cbfs prefix"
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endchoice
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config CBFS_PREFIX
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string "CBFS prefix to use" if CBFS_PREFIX_DIY
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default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
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default "normal" if CBFS_PREFIX_NORMAL
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help
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Select the prefix to all files put into the image. It's "fallback"
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by default, "normal" is a common alternative.
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choice
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prompt "Compiler to use"
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default COMPILER_GCC
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help
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This option allows you to select the compiler used for building
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coreboot.
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You must build the coreboot crosscompiler for the board that you
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have selected.
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To build all the GCC crosscompilers (takes a LONG time), run:
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make crossgcc
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For help on individual architectures, run the command:
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make help_toolchain
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config COMPILER_GCC
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bool "GCC"
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help
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Use the GNU Compiler Collection (GCC) to build coreboot.
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For details see http://gcc.gnu.org.
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config COMPILER_LLVM_CLANG
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bool "LLVM/clang (TESTING ONLY - Not currently working)"
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help
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Use LLVM/clang to build coreboot. To use this, you must build the
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coreboot version of the clang compiler. Run the command
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make clang
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Note that this option is not currently working correctly and should
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really only be selected if you're trying to work on getting clang
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operational.
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For details see http://clang.llvm.org.
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endchoice
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config ANY_TOOLCHAIN
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bool "Allow building with any toolchain"
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default n
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help
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Many toolchains break when building coreboot since it uses quite
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unusual linker features. Unless developers explicitely request it,
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we'll have to assume that they use their distro compiler by mistake.
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Make sure that using patched compilers is a conscious decision.
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config CCACHE
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bool "Use ccache to speed up (re)compilation"
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default n
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help
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Enables the use of ccache for faster builds.
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Requires the ccache utility in your system $PATH.
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For details see https://ccache.samba.org.
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config FMD_GENPARSER
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bool "Generate flashmap descriptor parser using flex and bison"
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default n
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help
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Enable this option if you are working on the flashmap descriptor
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parser and made changes to fmd_scanner.l or fmd_parser.y.
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Otherwise, say N to use the provided pregenerated scanner/parser.
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config UTIL_GENPARSER
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bool "Generate SCONFIG & BINCFG parser using flex and bison"
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default n
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help
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Enable this option if you are working on the sconfig device tree
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parser or bincfg and made changes to the .l or .y files.
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Otherwise, say N to use the provided pregenerated scanner/parser.
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config USE_OPTION_TABLE
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bool "Use CMOS for configuration values"
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depends on HAVE_OPTION_TABLE
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help
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Enable this option if coreboot shall read options from the "CMOS"
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NVRAM instead of using hard-coded values.
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config STATIC_OPTION_TABLE
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bool "Load default configuration values into CMOS on each boot"
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depends on USE_OPTION_TABLE
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help
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Enable this option to reset "CMOS" NVRAM values to default on
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every boot. Use this if you want the NVRAM configuration to
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never be modified from its default values.
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config COMPRESS_RAMSTAGE
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bool "Compress ramstage with LZMA"
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depends on HAVE_RAMSTAGE
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# Default value set at the end of the file
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help
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Compress ramstage to save memory in the flash image.
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config COMPRESS_PRERAM_STAGES
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bool "Compress romstage and verstage with LZ4"
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depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
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# Default value set at the end of the file
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help
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Compress romstage and (if it exists) verstage with LZ4 to save flash
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space and speed up boot, since the time for reading the image from SPI
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(and in the vboot case verifying it) is usually much greater than the
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time spent decompressing. Doesn't work for XIP stages (assume all
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ARCH_X86 for now) for obvious reasons.
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config COMPRESS_BOOTBLOCK
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bool
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depends on HAVE_BOOTBLOCK
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help
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This option can be used to compress the bootblock with LZ4 and attach
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a small self-decompression stub to its front. This can drastically
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reduce boot time on platforms where the bootblock is loaded over a
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very slow connection and bootblock size trumps all other factors for
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speed. Since using this option usually requires changes to the
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SoC memlayout and possibly extra support code, it should not be
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user-selectable. (There's no real point in offering this to the user
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anyway... if it works and saves boot time, you would always want it.)
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config INCLUDE_CONFIG_FILE
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bool "Include the coreboot .config file into the ROM image"
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# Default value set at the end of the file
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help
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Include the .config file that was used to compile coreboot
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in the (CBFS) ROM image. This is useful if you want to know which
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options were used to build a specific coreboot.rom image.
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Saying Y here will increase the image size by 2-3KB.
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You can use the following command to easily list the options:
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grep -a CONFIG_ coreboot.rom
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Alternatively, you can also use cbfstool to print the image
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contents (including the raw 'config' item we're looking for).
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Example:
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$ cbfstool coreboot.rom print
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coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
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offset 0x0
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Alignment: 64 bytes
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Name Offset Type Size
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cmos_layout.bin 0x0 CMOS layout 1159
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fallback/romstage 0x4c0 stage 339756
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fallback/ramstage 0x53440 stage 186664
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fallback/payload 0x80dc0 payload 51526
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config 0x8d740 raw 3324
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(empty) 0x8e480 null 3610440
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config COLLECT_TIMESTAMPS
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bool "Create a table of timestamps collected during boot"
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default y if ARCH_X86
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help
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Make coreboot create a table of timer-ID/timer-value pairs to
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allow measuring time spent at different phases of the boot process.
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config TIMESTAMPS_ON_CONSOLE
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bool "Print the timestamp values on the console"
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default n
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depends on COLLECT_TIMESTAMPS
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help
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Print the timestamps to the debug console if enabled at level info.
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config USE_BLOBS
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bool "Allow use of binary-only repository"
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default y
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help
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This draws in the blobs repository, which contains binary files that
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might be required for some chipsets or boards.
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This flag ensures that a "Free" option remains available for users.
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config USE_AMD_BLOBS
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bool "Allow AMD blobs repository (with license agreement)"
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depends on USE_BLOBS
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help
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This draws in the amd_blobs repository, which contains binary files
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distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
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etc. Selecting this item to download or clone the repo implies your
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agreement to the AMD license agreement. A copy of the license text
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may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
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and your copy of the license is present in the repo once downloaded.
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Note that for some products, omitting PSP, SMU images, or other items
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may result in a nonbooting coreboot.rom.
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config USE_QC_BLOBS
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bool "Allow QC blobs repository (selecting this agrees to the license!)"
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depends on USE_BLOBS
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help
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This draws in the qc_blobs repository, which contains binary files
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distributed by Qualcomm that are required to build firmware for
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certain Qualcomm SoCs (including QcLib, QC-SEC, qtiseclib and QUP
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firmware). If you say Y here you are implicitly agreeing to the
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Qualcomm license agreement which can be found at:
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https://review.coreboot.org/cgit/qc_blobs.git/tree/LICENSE
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*****************************************************
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PLEASE MAKE SURE YOU READ AND AGREE TO ALL TERMS IN
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ABOVE LICENSE AGREEMENT BEFORE SELECTING THIS OPTION!
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*****************************************************
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Not selecting this option means certain Qualcomm SoCs and related
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mainboards cannot be built and will be hidden from the "Mainboards"
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section.
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config COVERAGE
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bool "Code coverage support"
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depends on COMPILER_GCC
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help
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Add code coverage support for coreboot. This will store code
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coverage information in CBMEM for extraction from user space.
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If unsure, say N.
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config UBSAN
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bool "Undefined behavior sanitizer support"
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default n
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help
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Instrument the code with checks for undefined behavior. If unsure,
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say N because it adds a small performance penalty and may abort
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on code that happens to work in spite of the UB.
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config HAVE_ASAN_IN_ROMSTAGE
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bool
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default n
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config ASAN_IN_ROMSTAGE
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bool
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default n
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help
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Enable address sanitizer in romstage for platform.
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config HAVE_ASAN_IN_RAMSTAGE
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bool
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default n
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config ASAN_IN_RAMSTAGE
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bool
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default n
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help
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Enable address sanitizer in ramstage for platform.
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config ASAN
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bool "Address sanitizer support"
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default n
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select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE
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select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE
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help
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Enable address sanitizer - runtime memory debugger,
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designed to find out-of-bounds accesses and use-after-scope bugs.
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This feature consumes up to 1/8 of available memory and brings about
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~1.5x performance slowdown.
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If unsure, say N.
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if ASAN
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comment "Before using this feature, make sure that "
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comment "asan_shadow_offset_callback patch is applied to GCC."
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endif
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choice
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prompt "Stage Cache for ACPI S3 resume"
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default NO_STAGE_CACHE if !HAVE_ACPI_RESUME
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default TSEG_STAGE_CACHE if SMM_TSEG
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config NO_STAGE_CACHE
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bool "Disabled"
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help
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Do not save any component in stage cache for resume path. On resume,
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all components would be read back from CBFS again.
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config TSEG_STAGE_CACHE
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bool "TSEG"
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depends on SMM_TSEG
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help
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The option enables stage cache support for platform. Platform
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can stash copies of postcar, ramstage and raw runtime data
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inside SMM TSEG, to be restored on S3 resume path.
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config CBMEM_STAGE_CACHE
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bool "CBMEM"
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depends on !SMM_TSEG
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help
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The option enables stage cache support for platform. Platform
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can stash copies of postcar, ramstage and raw runtime data
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inside CBMEM.
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While the approach is faster than reloading stages from boot media
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it is also a possible attack scenario via which OS can possibly
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circumvent SMM locks and SPI write protections.
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If unsure, select 'N'
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endchoice
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config UPDATE_IMAGE
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bool "Update existing coreboot.rom image"
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help
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If this option is enabled, no new coreboot.rom file
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is created. Instead it is expected that there already
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is a suitable file for further processing.
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The bootblock will not be modified.
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If unsure, select 'N'
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config BOOTSPLASH_IMAGE
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bool "Add a bootsplash image"
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help
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Select this option if you have a bootsplash image that you would
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like to add to your ROM.
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This will only add the image to the ROM. To actually run it check
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options under 'Display' section.
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config BOOTSPLASH_FILE
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string "Bootsplash path and filename"
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depends on BOOTSPLASH_IMAGE
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# Default value set at the end of the file
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help
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The path and filename of the file to use as graphical bootsplash
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screen. The file format has to be jpg.
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config FW_CONFIG
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bool "Firmware Configuration Probing"
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default n
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help
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Enable support for probing devices with fw_config. This is a simple
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bitmask broken into fields and options for probing.
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config FW_CONFIG_SOURCE_CBFS
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bool "Obtain Firmware Configuration value from CBFS"
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depends on FW_CONFIG
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default n
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help
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With this option enabled coreboot will look for the 32bit firmware
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configuration value in CBFS at the selected prefix with the file name
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"fw_config". This option will override other sources and allow the
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local image to preempt the mainboard selected source.
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config FW_CONFIG_SOURCE_CHROMEEC_CBI
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bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
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depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
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default n
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help
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This option tells coreboot to read the firmware configuration value
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from the Google Chrome Embedded Controller CBI interface. This source
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is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
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found in CBFS.
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config HAVE_RAMPAYLOAD
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bool
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config RAMPAYLOAD
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bool "Enable coreboot flow without executing ramstage"
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default y if ARCH_X86
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depends on HAVE_RAMPAYLOAD
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help
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If this option is enabled, coreboot flow will skip ramstage
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loading and execution of ramstage to load payload.
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Instead it is expected to load payload from postcar stage itself.
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In this flow coreboot will perform basic x86 initialization
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(DRAM resource allocation), MTRR programming,
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Skip PCI enumeration logic and only allocate BAR for fixed devices
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(bootable devices, TPM over GSPI).
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config HAVE_CONFIGURABLE_RAMSTAGE
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bool
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config CONFIGURABLE_RAMSTAGE
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bool "Enable a configurable ramstage."
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default y if ARCH_X86
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depends on HAVE_CONFIGURABLE_RAMSTAGE
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help
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A configurable ramstage allows you to select which parts of the ramstage
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to run. Currently, we can only select a minimal PCI scanning step.
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The minimal PCI scanning will only check those parts that are enabled
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in the devicetree.cb. By convention none of those devices should be bridges.
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config MINIMAL_PCI_SCANNING
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bool "Enable minimal PCI scanning"
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depends on CONFIGURABLE_RAMSTAGE && PCI
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help
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If this option is enabled, coreboot will scan only PCI devices
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marked as mandatory in devicetree.cb
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endmenu
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menu "Mainboard"
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source "src/mainboard/Kconfig"
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config DEVICETREE
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string
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default "devicetree.cb"
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help
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This symbol allows mainboards to select a different file under their
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mainboard directory for the devicetree.cb file. This allows the board
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variants that need different devicetrees to be in the same directory.
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Examples: "devicetree.variant.cb"
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"variant/devicetree.cb"
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config OVERRIDE_DEVICETREE
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string
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default ""
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help
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This symbol allows variants to provide an override devicetree file to
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override the registers and/or add new devices on top of the ones
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provided by baseboard devicetree using CONFIG_DEVICETREE.
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Examples: "devicetree.variant-override.cb"
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"variant/devicetree-override.cb"
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config FMDFILE
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string "fmap description file in fmd format"
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
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default ""
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help
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The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
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but in some cases more complex setups are required.
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When an fmd is specified, it overrides the default format.
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config CBFS_SIZE
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hex "Size of CBFS filesystem in ROM"
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depends on FMDFILE = ""
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# Default value set at the end of the file
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help
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This is the part of the ROM actually managed by CBFS, located at the
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end of the ROM (passed through cbfstool -o) on x86 and at at the start
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of the ROM (passed through cbfstool -s) everywhere else. It defaults
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to span the whole ROM on all but Intel systems that use an Intel Firmware
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Descriptor. It can be overridden to make coreboot live alongside other
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components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
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binaries. This symbol should only be used to generate a default FMAP and
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is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
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endmenu
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# load site-local kconfig to allow user specific defaults and overrides
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source "site-local/Kconfig"
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config SYSTEM_TYPE_LAPTOP
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default n
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bool
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config SYSTEM_TYPE_TABLET
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default n
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bool
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config SYSTEM_TYPE_DETACHABLE
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default n
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bool
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config SYSTEM_TYPE_CONVERTIBLE
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default n
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bool
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config CBFS_AUTOGEN_ATTRIBUTES
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default n
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bool
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help
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If this option is selected, every file in cbfs which has a constraint
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regarding position or alignment will get an additional file attribute
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which describes this constraint.
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menu "Chipset"
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comment "SoC"
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source "src/soc/*/Kconfig"
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comment "CPU"
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source "src/cpu/Kconfig"
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comment "Northbridge"
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source "src/northbridge/*/*/Kconfig"
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source "src/northbridge/*/*/Kconfig.common"
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comment "Southbridge"
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source "src/southbridge/*/*/Kconfig"
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source "src/southbridge/*/*/Kconfig.common"
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comment "Super I/O"
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source "src/superio/*/*/Kconfig"
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comment "Embedded Controllers"
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source "src/ec/acpi/Kconfig"
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source "src/ec/*/*/Kconfig"
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source "src/southbridge/intel/common/firmware/Kconfig"
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source "src/vendorcode/*/Kconfig"
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source "src/arch/*/Kconfig"
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config CHIPSET_DEVICETREE
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string
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default ""
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help
|
|
This symbol allows a chipset to provide a set of default settings in
|
|
a devicetree which are common to all mainboards. This may include
|
|
devices (including alias names), chip drivers, register settings,
|
|
and others. This path is relative to the src/ directory.
|
|
|
|
Example: "chipset.cb"
|
|
|
|
endmenu
|
|
|
|
source "src/device/Kconfig"
|
|
|
|
menu "Generic Drivers"
|
|
source "src/drivers/*/Kconfig"
|
|
source "src/drivers/*/*/Kconfig"
|
|
source "src/drivers/*/*/*/Kconfig"
|
|
source "src/commonlib/storage/Kconfig"
|
|
endmenu
|
|
|
|
menu "Security"
|
|
|
|
source "src/security/Kconfig"
|
|
source "src/vendorcode/eltan/security/Kconfig"
|
|
|
|
endmenu
|
|
|
|
source "src/acpi/Kconfig"
|
|
|
|
# This option is for the current boards/chipsets where SPI flash
|
|
# is not the boot device. Currently nearly all boards/chipsets assume
|
|
# SPI flash is the boot device.
|
|
config BOOT_DEVICE_NOT_SPI_FLASH
|
|
bool
|
|
default n
|
|
|
|
config BOOT_DEVICE_SPI_FLASH
|
|
bool
|
|
default y if !BOOT_DEVICE_NOT_SPI_FLASH
|
|
default n
|
|
|
|
config BOOT_DEVICE_MEMORY_MAPPED
|
|
bool
|
|
default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
|
|
default n
|
|
help
|
|
Inform system if SPI is memory-mapped or not.
|
|
|
|
config BOOT_DEVICE_SUPPORTS_WRITES
|
|
bool
|
|
default n
|
|
help
|
|
Indicate that the platform has writable boot device
|
|
support.
|
|
|
|
config RTC
|
|
bool
|
|
default n
|
|
|
|
config HEAP_SIZE
|
|
hex
|
|
default 0x100000 if FLATTENED_DEVICE_TREE
|
|
default 0x4000
|
|
|
|
config STACK_SIZE
|
|
hex
|
|
default 0x1000 if ARCH_X86
|
|
default 0x0
|
|
|
|
config MAX_CPUS
|
|
int
|
|
default 1
|
|
|
|
source "src/console/Kconfig"
|
|
|
|
config HAVE_ACPI_RESUME
|
|
bool
|
|
default n
|
|
|
|
config DISABLE_ACPI_HIBERNATE
|
|
bool
|
|
default n
|
|
help
|
|
Removes S4 from the available sleepstates
|
|
|
|
config RESUME_PATH_SAME_AS_BOOT
|
|
bool
|
|
default y if ARCH_X86
|
|
depends on HAVE_ACPI_RESUME
|
|
help
|
|
This option indicates that when a system resumes it takes the
|
|
same path as a regular boot. e.g. an x86 system runs from the
|
|
reset vector at 0xfffffff0 on both resume and warm/cold boot.
|
|
|
|
config NO_MONOTONIC_TIMER
|
|
def_bool n
|
|
|
|
config HAVE_MONOTONIC_TIMER
|
|
bool
|
|
depends on !NO_MONOTONIC_TIMER
|
|
default y
|
|
help
|
|
The board/chipset provides a monotonic timer.
|
|
|
|
config GENERIC_UDELAY
|
|
bool
|
|
depends on HAVE_MONOTONIC_TIMER
|
|
default y if !ARCH_X86
|
|
help
|
|
The board/chipset uses a generic udelay function utilizing the
|
|
monotonic timer.
|
|
|
|
config TIMER_QUEUE
|
|
def_bool n
|
|
depends on HAVE_MONOTONIC_TIMER
|
|
help
|
|
Provide a timer queue for performing time-based callbacks.
|
|
|
|
config COOP_MULTITASKING
|
|
def_bool n
|
|
depends on TIMER_QUEUE && ARCH_X86
|
|
help
|
|
Cooperative multitasking allows callbacks to be multiplexed on the
|
|
main thread of ramstage. With this enabled it allows for multiple
|
|
execution paths to take place when they have udelay() calls within
|
|
their code.
|
|
|
|
config NUM_THREADS
|
|
int
|
|
default 4
|
|
depends on COOP_MULTITASKING
|
|
help
|
|
How many execution threads to cooperatively multitask with.
|
|
|
|
config HAVE_OPTION_TABLE
|
|
bool
|
|
default n
|
|
help
|
|
This variable specifies whether a given board has a cmos.layout
|
|
file containing NVRAM/CMOS bit definitions.
|
|
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
|
|
|
|
config PCI_IO_CFG_EXT
|
|
bool
|
|
default n
|
|
|
|
config IOAPIC
|
|
bool
|
|
default n
|
|
|
|
config USE_WATCHDOG_ON_BOOT
|
|
bool
|
|
default n
|
|
|
|
config GFXUMA
|
|
bool
|
|
default n
|
|
help
|
|
Enable Unified Memory Architecture for graphics.
|
|
|
|
config HAVE_MP_TABLE
|
|
bool
|
|
help
|
|
This variable specifies whether a given board has MP table support.
|
|
It is usually set in mainboard/*/Kconfig.
|
|
Whether or not the MP table is actually generated by coreboot
|
|
is configurable by the user via GENERATE_MP_TABLE.
|
|
|
|
config HAVE_PIRQ_TABLE
|
|
bool
|
|
help
|
|
This variable specifies whether a given board has PIRQ table support.
|
|
It is usually set in mainboard/*/Kconfig.
|
|
Whether or not the PIRQ table is actually generated by coreboot
|
|
is configurable by the user via GENERATE_PIRQ_TABLE.
|
|
|
|
config ACPI_NHLT
|
|
bool
|
|
default n
|
|
help
|
|
Build support for NHLT (non HD Audio) ACPI table generation.
|
|
|
|
#These Options are here to avoid "undefined" warnings.
|
|
#The actual selection and help texts are in the following menu.
|
|
|
|
menu "System tables"
|
|
|
|
config GENERATE_MP_TABLE
|
|
prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
|
|
bool
|
|
default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
|
|
help
|
|
Generate an MP table (conforming to the Intel MultiProcessor
|
|
specification 1.4) for this board.
|
|
|
|
If unsure, say Y.
|
|
|
|
config GENERATE_PIRQ_TABLE
|
|
prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
|
|
bool
|
|
default HAVE_PIRQ_TABLE
|
|
help
|
|
Generate a PIRQ table for this board.
|
|
|
|
If unsure, say Y.
|
|
|
|
config GENERATE_SMBIOS_TABLES
|
|
depends on ARCH_X86
|
|
bool "Generate SMBIOS tables"
|
|
default y
|
|
help
|
|
Generate SMBIOS tables for this board.
|
|
|
|
If unsure, say Y.
|
|
|
|
config SMBIOS_PROVIDED_BY_MOBO
|
|
bool
|
|
default n
|
|
|
|
config MAINBOARD_SERIAL_NUMBER
|
|
prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
|
|
string
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
default "123456789"
|
|
help
|
|
The Serial Number to store in SMBIOS structures.
|
|
|
|
config MAINBOARD_VERSION
|
|
prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
|
|
string
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
default "1.0"
|
|
help
|
|
The Version Number to store in SMBIOS structures.
|
|
|
|
config MAINBOARD_SMBIOS_MANUFACTURER
|
|
prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
|
|
string
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
default MAINBOARD_VENDOR
|
|
help
|
|
Override the default Manufacturer stored in SMBIOS structures.
|
|
|
|
config MAINBOARD_SMBIOS_PRODUCT_NAME
|
|
prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
|
|
string
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
default MAINBOARD_PART_NUMBER
|
|
help
|
|
Override the default Product name stored in SMBIOS structures.
|
|
|
|
config VPD_SMBIOS_VERSION
|
|
bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'"
|
|
default n
|
|
depends on VPD && GENERATE_SMBIOS_TABLES
|
|
help
|
|
Selecting this option will read firmware_version from
|
|
VPD_RO and override SMBIOS type 0 version. One special
|
|
scenario of using this feature is to assign a BIOS version
|
|
to a coreboot image without the need to rebuild from source.
|
|
|
|
endmenu
|
|
|
|
source "payloads/Kconfig"
|
|
|
|
menu "Debugging"
|
|
|
|
comment "CPU Debug Settings"
|
|
source "src/cpu/*/Kconfig.debug_cpu"
|
|
|
|
comment "BLOB Debug Settings"
|
|
source "src/drivers/intel/fsp*/Kconfig.debug_blob"
|
|
|
|
comment "General Debug Settings"
|
|
|
|
# TODO: Better help text and detailed instructions.
|
|
config GDB_STUB
|
|
bool "GDB debugging support"
|
|
default n
|
|
depends on DRIVERS_UART
|
|
help
|
|
If enabled, you will be able to set breakpoints for gdb debugging.
|
|
See src/arch/x86/lib/c_start.S for details.
|
|
|
|
config GDB_WAIT
|
|
bool "Wait for a GDB connection in the ramstage"
|
|
default n
|
|
depends on GDB_STUB
|
|
help
|
|
If enabled, coreboot will wait for a GDB connection in the ramstage.
|
|
|
|
|
|
config FATAL_ASSERTS
|
|
bool "Halt when hitting a BUG() or assertion error"
|
|
default n
|
|
help
|
|
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
|
|
|
|
config HAVE_DEBUG_GPIO
|
|
bool
|
|
|
|
config DEBUG_GPIO
|
|
bool "Output verbose GPIO debug messages"
|
|
depends on HAVE_DEBUG_GPIO
|
|
|
|
config DEBUG_CBFS
|
|
bool "Output verbose CBFS debug messages"
|
|
default n
|
|
help
|
|
This option enables additional CBFS related debug messages.
|
|
|
|
config HAVE_DEBUG_RAM_SETUP
|
|
def_bool n
|
|
|
|
config DEBUG_RAM_SETUP
|
|
bool "Output verbose RAM init debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_RAM_SETUP
|
|
help
|
|
This option enables additional RAM init related debug messages.
|
|
It is recommended to enable this when debugging issues on your
|
|
board which might be RAM init related.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_PIRQ
|
|
bool "Check PIRQ table consistency"
|
|
default n
|
|
depends on GENERATE_PIRQ_TABLE
|
|
help
|
|
If unsure, say N.
|
|
|
|
config HAVE_DEBUG_SMBUS
|
|
def_bool n
|
|
|
|
config DEBUG_SMBUS
|
|
bool "Output verbose SMBus debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_SMBUS
|
|
help
|
|
This option enables additional SMBus (and SPD) debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SMI
|
|
bool "Output verbose SMI debug messages"
|
|
default n
|
|
depends on HAVE_SMI_HANDLER
|
|
select SPI_FLASH_SMM if EM100PRO_SPI_CONSOLE || CONSOLE_SPI_FLASH
|
|
help
|
|
This option enables additional SMI related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_PERIODIC_SMI
|
|
bool "Trigger SMI periodically"
|
|
depends on DEBUG_SMI
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config DEBUG_MALLOC
|
|
prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
|
|
bool
|
|
default n
|
|
help
|
|
This option enables additional malloc related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
# Only visible if DEBUG_SPEW (8) is set.
|
|
config DEBUG_RESOURCES
|
|
bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
|
|
default n
|
|
help
|
|
This option enables additional PCI memory and IO debug messages.
|
|
Note: This option will increase the size of the coreboot image.
|
|
If unsure, say N.
|
|
|
|
config DEBUG_CONSOLE_INIT
|
|
bool "Debug console initialisation code"
|
|
default n
|
|
help
|
|
With this option printk()'s are attempted before console hardware
|
|
initialisation has been completed. Your mileage may vary.
|
|
|
|
Typically you will need to modify source in console_hw_init() such
|
|
that a working console appears before the one you want to debug.
|
|
|
|
If unsure, say N.
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config REALMODE_DEBUG
|
|
prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
|
|
bool
|
|
default n
|
|
depends on PCI_OPTION_ROM_RUN_REALMODE
|
|
help
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
Note: This option will increase the time to emulate a ROM.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG
|
|
bool "Output verbose x86emu debug messages"
|
|
default n
|
|
depends on PCI_OPTION_ROM_RUN_YABEL
|
|
help
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_JMP
|
|
bool "Trace JMP/RETF"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print information about JMP and RETF opcodes from x86emu.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_TRACE
|
|
bool "Trace all opcodes"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print _all_ opcodes that are executed by x86emu.
|
|
|
|
WARNING: This will produce a LOT of output and take a long time.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_PNP
|
|
bool "Log Plug&Play accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print Plug And Play accesses made by option ROMs.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_DISK
|
|
bool "Log Disk I/O"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print Disk I/O related messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_PMM
|
|
bool "Log PMM"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to POST Memory Manager (PMM).
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
config X86EMU_DEBUG_VBE
|
|
bool "Debug VESA BIOS Extensions"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to VESA BIOS Extension (VBE) functions.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_INT10
|
|
bool "Redirect INT10 output to console"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Let INT10 (i.e. character output) calls print messages to debug output.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_INTERRUPTS
|
|
bool "Log intXX calls"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to interrupt handling.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_CHECK_VMEM_ACCESS
|
|
bool "Log special memory accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to accesses to certain areas of the virtual
|
|
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_MEM
|
|
bool "Log all memory accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print memory accesses made by option ROM.
|
|
Note: This also includes accesses to fetch instructions.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_IO
|
|
bool "Log IO accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print I/O accesses made by option ROM.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_TIMINGS
|
|
bool "Output timing information"
|
|
default n
|
|
depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
|
|
help
|
|
Print timing information needed by i915tool.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SPI_FLASH
|
|
bool "Output verbose SPI flash debug messages"
|
|
default n
|
|
depends on SPI_FLASH
|
|
help
|
|
This option enables additional SPI flash related debug messages.
|
|
|
|
config DEBUG_IPMI
|
|
bool "Output verbose IPMI debug messages"
|
|
default n
|
|
depends on IPMI_KCS
|
|
help
|
|
This option enables additional IPMI related debug messages.
|
|
|
|
if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
|
|
# Only visible with the right southbridge and loglevel.
|
|
config DEBUG_INTEL_ME
|
|
bool "Verbose logging for Intel Management Engine"
|
|
default n
|
|
help
|
|
Enable verbose logging for Intel Management Engine driver that
|
|
is present on Intel 6-series chipsets.
|
|
endif
|
|
|
|
config DEBUG_FUNC
|
|
bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8
|
|
default n
|
|
help
|
|
This option enables additional function entry and exit debug messages
|
|
for select functions.
|
|
Note: This option will increase the size of the coreboot image.
|
|
If unsure, say N.
|
|
|
|
config DEBUG_COVERAGE
|
|
bool "Debug code coverage"
|
|
default n
|
|
depends on COVERAGE
|
|
help
|
|
If enabled, the code coverage hooks in coreboot will output some
|
|
information about the coverage data that is dumped.
|
|
|
|
config DEBUG_BOOT_STATE
|
|
bool "Debug boot state machine"
|
|
default n
|
|
help
|
|
Control debugging of the boot state machine. When selected displays
|
|
the state boundaries in ramstage.
|
|
|
|
config DEBUG_ADA_CODE
|
|
bool "Compile debug code in Ada sources"
|
|
default n
|
|
help
|
|
Add the compiler switch `-gnata` to compile code guarded by
|
|
`pragma Debug`.
|
|
|
|
config HAVE_EM100_SUPPORT
|
|
bool "Platform can support the Dediprog EM100 SPI emulator"
|
|
help
|
|
This is enabled by platforms which can support using the EM100.
|
|
|
|
config EM100
|
|
bool "Configure image for EM100 usage"
|
|
depends on HAVE_EM100_SUPPORT
|
|
help
|
|
The Dediprog EM100 SPI emulator allows fast loading of new SPI images
|
|
over USB. However it only supports a maximum SPI clock of 20MHz and
|
|
single data output. Enable this option to use a 20MHz SPI clock and
|
|
disable "Dual Output Fast Read" Support.
|
|
|
|
On AMD platforms this changes the SPI speed at run-time if the
|
|
mainboard code supports this. On supported Intel platforms this works
|
|
by changing the settings in the descriptor.bin file.
|
|
|
|
endmenu
|
|
|
|
###############################################################################
|
|
# Set variables with no prompt - these can be set anywhere, and putting at
|
|
# the end of this file gives the most flexibility.
|
|
|
|
source "src/lib/Kconfig"
|
|
|
|
config WARNINGS_ARE_ERRORS
|
|
bool
|
|
default y
|
|
|
|
# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
|
|
# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
|
|
# mutually exclusive. One of these options must be selected in the
|
|
# mainboard Kconfig if the chipset supports enabling and disabling of
|
|
# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
|
|
# in mainboard/Kconfig to know if the button should be enabled or not.
|
|
|
|
config POWER_BUTTON_DEFAULT_ENABLE
|
|
def_bool n
|
|
help
|
|
Select when the board has a power button which can optionally be
|
|
disabled by the user.
|
|
|
|
config POWER_BUTTON_DEFAULT_DISABLE
|
|
def_bool n
|
|
help
|
|
Select when the board has a power button which can optionally be
|
|
enabled by the user, e.g. when the board ships with a jumper over
|
|
the power switch contacts.
|
|
|
|
config POWER_BUTTON_FORCE_ENABLE
|
|
def_bool n
|
|
help
|
|
Select when the board requires that the power button is always
|
|
enabled.
|
|
|
|
config POWER_BUTTON_FORCE_DISABLE
|
|
def_bool n
|
|
help
|
|
Select when the board requires that the power button is always
|
|
disabled, e.g. when it has been hardwired to ground.
|
|
|
|
config POWER_BUTTON_IS_OPTIONAL
|
|
bool
|
|
default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
|
|
default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
|
|
help
|
|
Internal option that controls ENABLE_POWER_BUTTON visibility.
|
|
|
|
config REG_SCRIPT
|
|
bool
|
|
default n
|
|
help
|
|
Internal option that controls whether we compile in register scripts.
|
|
|
|
config MAX_REBOOT_CNT
|
|
int
|
|
default 3
|
|
help
|
|
Internal option that sets the maximum number of bootblock executions allowed
|
|
with the normal image enabled before assuming the normal image is defective
|
|
and switching to the fallback image.
|
|
|
|
config UNCOMPRESSED_RAMSTAGE
|
|
bool
|
|
|
|
config NO_XIP_EARLY_STAGES
|
|
bool
|
|
default n if ARCH_X86
|
|
default y
|
|
help
|
|
Identify if early stages are eXecute-In-Place(XIP).
|
|
|
|
config EARLY_CBMEM_LIST
|
|
bool
|
|
default n
|
|
help
|
|
Enable display of CBMEM during romstage and postcar.
|
|
|
|
config RELOCATABLE_MODULES
|
|
bool
|
|
help
|
|
If RELOCATABLE_MODULES is selected then support is enabled for
|
|
building relocatable modules in the RAM stage. Those modules can be
|
|
loaded anywhere and all the relocations are handled automatically.
|
|
|
|
config GENERIC_GPIO_LIB
|
|
bool
|
|
help
|
|
If enabled, compile the generic GPIO library. A "generic" GPIO
|
|
implies configurability usually found on SoCs, particularly the
|
|
ability to control internal pull resistors.
|
|
|
|
config BOOTBLOCK_CUSTOM
|
|
# To be selected by arch, SoC or mainboard if it does not want use the normal
|
|
# src/lib/bootblock.c#main() C entry point.
|
|
bool
|
|
|
|
config MEMLAYOUT_LD_FILE
|
|
string
|
|
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld"
|
|
help
|
|
This variable allows SoC/mainboard to supply in a custom linker file
|
|
if required. This determines the linker file used for all the stages
|
|
(bootblock, romstage, verstage, ramstage, postcar) in
|
|
src/arch/${ARCH}/Makefile.inc.
|
|
|
|
###############################################################################
|
|
# Set default values for symbols created before mainboards. This allows the
|
|
# option to be displayed in the general menu, but the default to be loaded in
|
|
# the mainboard if desired.
|
|
config COMPRESS_RAMSTAGE
|
|
default y if !UNCOMPRESSED_RAMSTAGE
|
|
|
|
config COMPRESS_PRERAM_STAGES
|
|
depends on !ARCH_X86
|
|
default y
|
|
|
|
config INCLUDE_CONFIG_FILE
|
|
default y
|
|
|
|
config BOOTSPLASH_FILE
|
|
depends on BOOTSPLASH_IMAGE
|
|
default "bootsplash.jpg"
|
|
|
|
config CBFS_SIZE
|
|
default ROM_SIZE
|
|
|
|
config HAVE_BOOTBLOCK
|
|
bool
|
|
default y
|
|
|
|
config HAVE_VERSTAGE
|
|
bool
|
|
depends on VBOOT_SEPARATE_VERSTAGE
|
|
default y
|
|
|
|
config HAVE_ROMSTAGE
|
|
bool
|
|
default y
|
|
|
|
config HAVE_RAMSTAGE
|
|
bool
|
|
default n if RAMPAYLOAD
|
|
default y
|