0f718312f1
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required. BUG=None BRANCH=None TEST=Boot to ChromeOS. Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
123 lines
3.2 KiB
C
123 lines
3.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootstate.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <elog.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/xhci.h>
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#include <soc/pm.h>
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#include <soc/pci_devs.h>
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#include <soc/smbus.h>
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#include <stdint.h>
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static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
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{
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int i;
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gpe0_sts &= gpe0_en;
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for (i = 0; i <= 31; i++) {
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if (gpe0_sts & (1 << i))
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elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start);
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}
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}
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static void pch_log_wake_source(struct chipset_power_state *ps)
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{
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/* Power Button */
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if (ps->pm1_sts & PWRBTN_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
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/* RTC */
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if (ps->pm1_sts & RTC_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
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/* PCI Express (TODO: determine wake device) */
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if (ps->pm1_sts & PCIEXPWAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
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/* PME */
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if (ps->gpe0_sts[GPE0_A] & CSE_PME_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
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/* XHCI */
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if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS)
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pch_xhci_update_wake_event(soc_get_xhci_usb_info());
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/* SMBUS Wake */
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if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS)
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elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
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/* ACPI Wake Event - Log prev sleep state only if it was not S0. */
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if (ps->prev_sleep_state != ACPI_S0)
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elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
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/* Log GPIO events in set A-D */
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pch_log_gpio_gpe(ps->gpe0_sts[GPE0_A], ps->gpe0_en[GPE0_A], 0);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE0_B], ps->gpe0_en[GPE0_B], 32);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE0_C], ps->gpe0_en[GPE0_C], 64);
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pch_log_gpio_gpe(ps->gpe0_sts[GPE0_D], ps->gpe0_en[GPE0_D], 96);
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}
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static void pch_log_power_and_resets(struct chipset_power_state *ps)
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{
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/* RTC Reset */
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if (ps->gen_pmcon1 & RPS)
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elog_add_event(ELOG_TYPE_RTC_RESET);
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/* System Reset */
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if (ps->gen_pmcon1 & WARM_RESET_STS)
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elog_add_event(ELOG_TYPE_SYSTEM_RESET);
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/* TCO Timeout */
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if (ps->prev_sleep_state != ACPI_S3 &&
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ps->tco1_sts & TCO_TIMEOUT)
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elog_add_event(ELOG_TYPE_TCO_RESET);
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/* Power Button Override */
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if (ps->pm1_sts & PRBTNOR_STS)
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elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
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}
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void pch_log_state(void)
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{
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struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
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if (ps == NULL) {
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printk(BIOS_ERR,
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"Not logging power state information. "
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"Power state not found in cbmem.\n");
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return;
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}
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/* Power and Reset */
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pch_log_power_and_resets(ps);
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/* Wake Sources */
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if (ps->prev_sleep_state > ACPI_S0)
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pch_log_wake_source(ps);
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}
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void elog_gsmi_cb_platform_log_wake_source(void)
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{
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struct chipset_power_state ps;
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pmc_fill_pm_reg_info(&ps);
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pch_log_wake_source(&ps);
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}
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