5672dcd58c
On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13706 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
32 lines
874 B
Makefile
32 lines
874 B
Makefile
ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cache_as_ram.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += gpio.c
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bootblock-y += mmap_boot.c
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bootblock-y += placeholders.c
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bootblock-y += tsc_freq.c
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bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += placeholders.c
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romstage-y += gpio.c
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romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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romstage-y += mmap_boot.c
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smm-y += placeholders.c
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ramstage-y += placeholders.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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ramstage-y += mmap_boot.c
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CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
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endif
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