coreboot-kgpe-d16/src/southbridge
Duncan Laurie 2d9d39a704 lynxpoint: Enable USB clock gating, late setup, and sleep prep
Both EHCI and XHCI controllers have additional setup steps
that are not part of the PEI reference code so they need to
be done later.

Both controllers also have specific clock gating setup
requirements that are now implemented.

Additionally they both have specific requirements when entering
sleep states.  XHCI needs something in S3/S4/S5 and EHCI only
has steps for S4/S5 entry.

Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4217
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:55:15 +01:00
..
amd AMD Hudson: Move function s3_resume_init_data to southbridge 2013-11-12 16:40:48 +01:00
broadcom x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
dmp dmp/vortex86ex: Move DMP specific POST code defines into one file 2013-11-24 05:36:36 +01:00
intel lynxpoint: Enable USB clock gating, late setup, and sleep prep 2013-11-25 23:55:15 +01:00
nvidia usbdebug: Fix boards without EARLY_CBMEM_INIT 2013-10-22 21:35:05 +02:00
rdc x86: Unify arch/io.h and arch/romcc_io.h 2013-03-22 00:00:09 +01:00
ricoh
sis usbdebug: Fix boards without EARLY_CBMEM_INIT 2013-10-22 21:35:05 +02:00
ti
via southbridge/via/vt8237r/ctrl.c: Remove set but unused variable regm3 2013-11-05 21:33:38 +01:00
Kconfig Add support for DMP Vortex86EX PCI southbridge. 2013-07-03 18:31:22 +02:00
Makefile.inc Add support for DMP Vortex86EX PCI southbridge. 2013-07-03 18:31:22 +02:00