Michael Niewöhner 569887a640 soc/intel/common: lpc/espi: fix wrong lock bit ... This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001. Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2019-10-18 14:55:35 +00:00
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amd	device: Use scan_static_bus() over scan_lpc_bus()	2019-10-08 12:59:56 +00:00
cavium	devicetree: Fix improper use of chip_operations	2019-10-04 16:29:31 +00:00
imgtec	cpu,mb,soc: Init missing lb_serial struct fields	2019-09-19 09:28:10 +00:00
intel	soc/intel/common: lpc/espi: fix wrong lock bit	2019-10-18 14:55:35 +00:00
mediatek	soc/mediatek/mt8183: Compress calibration blob with LZ4	2019-10-18 12:25:23 +00:00
nvidia	cpu,mb,soc: Init missing lb_serial struct fields	2019-09-19 09:28:10 +00:00
qualcomm	soc/qualcomm: Remove default ops to generate bootblock.bin	2019-10-09 22:24:56 +00:00
rockchip	arm64: Uprev Arm TF and adjust to BL31 parameter changes	2019-09-14 05:01:16 +00:00
samsung	cpu,mb,soc: Init missing lb_serial struct fields	2019-09-19 09:28:10 +00:00
sifive	soc/sifive/fu540: test and fix code of fu540 spi	2019-10-16 14:12:20 +00:00
ucb	lib: Rewrite qemu-armv7 ramdetect	2019-07-28 11:31:42 +00:00