Felix Held 57419de187 soc/amd/cezanne: add basic romstage ... This currently only initializes the console, calls into the FSP driver that then calls into FSP-M and then jumps to ramstage after the FSP-M returns. Right now, this mainly unblocks the FSP-M development. Change-Id: I9f3cdaac573e365bb4d59364d44727677f53e91b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>		2021-01-24 18:15:59 +00:00
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cezanne	soc/amd/cezanne: add basic romstage	2021-01-24 18:15:59 +00:00
common	ACPI: Add helpers for CBMEM_ID_POWER_STATE	2021-01-23 20:31:09 +00:00
picasso	soc/amd/picasso: Remove some empty strings	2021-01-24 18:10:31 +00:00
stoneyridge	soc/amd: Rename chipset_state to chipset_power_state	2021-01-23 20:21:14 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00